Analogue SSB Chip Other Saul Research 0.35 μm XH035 PT GDSII Very low power (3V, 25uA) 90 degree analogue phase shifter for SSB encoding/decoding. A full description is on the web site, with all measurements.
SA00AH8A00 ADC Sony LSI Design Inc. 0.35 μm XH035 ID GDSII SA00AH8A00 is a subranging 8-bit high-speed 50MS/s Analog-to-Digital Converter(ADC) for video band and disk servo use.
SA00AH8B00 ADC Sony LSI Design Inc. 0.35 μm XH035 ID GDSII SA00AH8B00 is a subranging 8-bit low-power 25MS/s Analog-to-Digital Converter(ADC) for disk servo use.
SA00PFC000 PLL Sony LSI Design Inc. 0.35 μm XH035 ID GDSII SA00PFC000 is a PLL with internal loop filter. Wide output clock freq. range : 10MHz～200MHz. Wide input clock freq. range : 2MHz～50MHz
SA00PFC010 PLL Sony LSI Design Inc. 0.35 μm XH035 ID GDSII SA00PFC010 is a PLL with internal loop filter. Wide output clock freq. range : 10MHz～160MHz. Wide input clock freq. range : 2.5MHz～6MHz.
SA00DJAA00 DAC Sony LSI Design Inc. 0.35 μm XH035 ID GDSII SA00DJAA00 is a high-speed 50MS/s Digital-to-Analog Converter(DAC) for video band use.
DT2120 ADC Digian Technology,Inc. 0.35 μm XH035 MP GDSII The dT2120 is designed featuring low-voltage and low-power mono ADC (Analog-to -Digital Converter) for sensor applications. The ADC architecture is using 4th-order 1bit sigma-delta modulator with 64-times oversampling. The dT2120’s in
CM1112ae Voltage Regulator chipus 0.35 μm XH035 MP GDSII General purpose linear voltage regulator. The circuit generates a 3.3V output voltage from an unregulated input voltage ranging from 5V to 30V. It features short circuit protection and 5mA output current capability.
CM1412ae Power on Reset chipus 0.35 μm XH035 MP GDSII 2Low consumption Power-On Reset (POR) core. The core has a voltage sense (configurable 0.9V - 5.5V), an internal current bias circuit and two configurable assertion delays (default are > 1μs and > 20μs). A configurable hysteresis (default 100mV).
CM1511ae Other chipus 0.35 μm XH035 MP GDSII Low consumption combo voltage and current reference core. The circuit generates an unbuffered 1.29V, temperature compensated voltage reference (70ppm/°C) and provides a 1.6μA PMOS current branch (200ppm/°C).
CM2013ae ADC chipus 0.35 μm XH035 PT GDSII Low power, general purpose, 10-bit, 50kSPS, Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) core. The circuit uses one 3.3V analog supply and one 3.3V digital supply and is targeted for microcontroller applications.
CM4013ae Oscillator chipus 0.35 μm XH035 MP GDSII General purpose, low power internal oscillator core, 12MHz. The circuit has internal level shifting and start-up circuits. A 4-bit digital bus allows frequency calibration against process variations. Current consumption <40μA, supply voltage 2.7V-3.6V
CM6011ae Other chipus 0.35 μm XH035 PT GDSII General purpose capacitive sensor core. The circuit is intended for touch sensing applications for use in microcontrollers and has two multiplexed inputs. 3pF input sensibility and output frequency of 460kHz - 600kHz.
CM6111ae Other chipus 0.35 μm XH035 PT GDSII 30V/20mA Power Driver/Switch - Two modes of operation: switch or programmable current output; short-circuit protection, over-current detection.
PWM Other Ridgetop Group 0.35 μm XH035 ID GDSII 250kHz PWM for DC-DC converters
High V Input Cell Other Ridgetop Group 0.35 μm XH035 ID GDSII High Voltage Input for input voltages up to 100V
LNA1 * LNA X-FAB 0.60 µm XB06 PT Schematic XB06: LNA library: RF_LNA_CELLS. LNA 1 is a low noise amplifier. It shoud be biased by the RF bias cell.
LNA2 * LNA X-FAB 0.60 µm XB06 PT Schematic XB06: LNA library: RF_LNA_CELLS. LNA2 is a low noise amplifier. It should be biased by the RF bias cell
LNA3 * LNA X-FAB 0.60 µm XB06 PT Schematic XB06: LNA library: RF_LNA_CELLS. LNA3 is a low noise amplifier with on-chip inductor. It should be biased by the RF bias cell.
LCVCO2 * VCO X-FAB 0.60 µm XB06 PT Schematic XB06: LNA library: RF_LCVCO_CELLS. LCVCO2 is a fully integrated LC-VCO. It should be biased by the RF bias cell. It is based on a cross-coupled bipolar transistor pair. It contains AC-coupled varactors and a special circuit technique for maintaining the D
LCVCO3 * VCO X-FAB 0.60 µm XB06 PT Schematic XB06: LNA library: RF_LCVCO_CELLS. LCVCO3 is a fully integrated LC-VCO. It should be biased by the RF bias cell. It contains a cross-coupled bipolar transistor pair and direct coupled varactors. For this reason, it has a higher tuning range than the other
RINGVCO1 * VCO X-FAB 0.60 µm XB06 PT Schematic XB06: LNA library: RF_VCO_CELLS. RINGVCO1 is a fully integrated VCO. It should be biased by the RF bias cell. It consists of a ringoscillator that is tuned by switching the delay chain between 2 and 4 delay stages. The transition between the two borders i
MIXER * Mixer X-FAB 0.60 µm XB06 PT Schematic XB06: LNA library: RF_MIXER_CELLS. MIXER is a down conversion mixer based on a Gilbert cell topology. It should be biased by the RF bias cell.
PA * Power Amplifiers X-FAB 0.60 µm XB06 PT Schematic XB06: LNA library: RF_PA_CELLS. PA is a non-linear Power Amplifier that is intended for the transmission of ASK and FSK signals. Its output power level can be digitally controlled in 4 steps. It should be biased by the RF bias cell.
DIV32 * Divider X-FAB 0.60 µm XB06 PT Schematic XB06: LNA library: RF_DIVIDER_CELLS. DIV32 is a Prescaler with a fixed divider ratio of 32. It should be biased by the RF bias cell.
BIAS * Bias X-FAB 0.60 µm XB06 PT Verilog XB06: LNA library: RF_BIAS_CELLS. BIAS is a bias cell intended for use with various RF building blocks. It is designed as a bandgap reference as well as voltage-to-current converter. Current biasing is preferable because of the higher immunity to interfer
OEIC_Fast * Optical Receiver Channel X-FAB 0.60 µm XB06 PT Schematic XB06: OEIC Building Block Library. OEIC_Fast is a fast DVD receiver channel with two selectable gain settings. Can be integrated with photodiode to form a complete optical receiver channel optimized for 660nm wavelengths.
OEIC_Sensitive * Optical Receiver Channel X-FAB 0.60 µm XB06 PT Schematic XB06: OEIC Building Block Library. OEIC_Sensitive is a sensitive DVD receiver channel with two selectable gain settings. Can be integrated with photodiode to form a complete optical receiver channel optimized for 660nm wavelengths.
DPIN * Integrated Photodiode X-FAB 0.60 µm XB06 PT Schematic XB06: OEIC Building Block Library. DPIN_5050 and DPIN_50100 are fast photodiodes with a vertical PIN structure optimized forred light (660nm).
aopac01 * Operational Amplifier X-FAB 0.60 µm XB06 PT Schematic XB06: A_CELLS. aopac01 is a low power internal frequency-compensated CMOS operational amplifier with pmos input stage
