acmpc01 *
Comparators
X-FAB
1.00 µm
XC10
PT
Analog Library Layout Schematic
XC10: A_CELLS; A_CELLS_M1. acmpc01 is a general purpose voltage comparator with P-MOS input and hysteresis.
acmpc03 *
Comparators
X-FAB
1.00 µm
XC10
PT
Analog Library Layout Schematic
XC10: A_CELLS; A_CELLS_M1. acmpc03 is a general purpose, low-consumption voltage comparator with N-MOS input.
acmpc04 *
Comparators
X-FAB
1.00 µm
XC10
PT
Analog Library Layout Schematic
XC10: A_CELLS; A_CELLS_M1. acmpc04 is a general purpose, low power voltage comparator with P-MOS input.
abgpc01 *
Bandgaps
X-FAB
1.00 µm
XC10
PT
Analog Library Layout Schematic
XC10: A_CELLS; A_CELLS_M1. abgpc01 is a bandgap reference with well resistors.
abgpc02 *
Bandgaps
X-FAB
1.00 µm
XC10
PT
Analog Library Layout Schematic
XC10: A_CELLS; A_CELLS_M1. abgpc02 is a bandgap reference with Poly2 resistors. The cell doesn’t include an output buffer.
abgpc03 *
Bandgaps
X-FAB
1.00 µm
XC10
PT
Analog Library Layout Schematic
XC10: A_CELLS; A_CELLS_M1. abgpc03 is a bandgap reference with Poly2 resistors. The cell doesn’t include an output buffer.
abiac01 *
Bias
X-FAB
1.00 µm
XC10
PT
Analog Library Layout Schematic
XC10: A_CELLS; A_CELLS_M1. abiac01 is a general purpose VTH - based current reference. The circuit forces a current of 2.4μA (approx.) to flow through P- or N-MOS transistor with a W/L ratio of 10μm/6μm.
abiac02 *
Bias
X-FAB
1.00 µm
XC10
PT
Analog Library Layout Schematic
XC10: A_CELLS; A_CELLS_M1. abiac02 is a general purpose weak inversion bias cell. The circuit forces a current of 250nA (approx.) to flow through P- or N-MOS transistors with a W/L ratio of 10μm/10μm.
achpc01 *
Charge Pumps
X-FAB
1.00 µm
XC10
PT
Analog Library Layout Schematic
XC10: A_CELLS; A_CELLS_M1. achpc01 is doubling charge pump 5V to 8.75V.
achpc02 *
Charge Pumps
X-FAB
1.00 µm
XC10
PT
Analog Library Layout Schematic
XC10: A_CELLS; A_CELLS_M1. achpc02 is a 4-stage Dickson charge pump originally designed for EEPROM.
arcoc01 *
Oscillator
X-FAB
1.00 µm
XC10
PT
Analog Library Layout Schematic
XC10: A_CELLS; A_CELLS_M1. arcoc01 is a 200kHz fixed frequency, current balancing RC oscillator with internal R and C.
arcoc02 *
Oscillator
X-FAB
1.00 µm
XC10
PT
Analog Library Layout Schematic
XC10: A_CELLS; A_CELLS_M1. arcoc02 is a 200kHz adjustable current balancing RC oscillator with internal R and C.
arcoc03 *
Oscillator
X-FAB
1.00 µm
XC10
PT
Analog Library Layout Schematic
XC10: A_CELLS; A_CELLS_M1. arcoc03 is a 1MHz fixed frequency, current balancing RC oscillator with internal R and C.
arcoc04 *
Oscillator
X-FAB
1.00 µm
XC10
PT
Analog Library Layout Schematic
XC10: A_CELLS; A_CELLS_M1. arcoc04 is a 1MHz an adjustable current balancing RC oscillator with internal R and C.
arcoc05 *
Oscillator
X-FAB
1.00 µm
XC10
PT
Analog Library Layout Schematic
XC10: A_CELLS; A_CELLS_M1. arcoc05 is a 10kHz RC oscillator with internal R and C. The cell is suitable for applications that do not require high stability.
arcoc06 *
Oscillator
X-FAB
1.00 µm
XC10
PT
Analog Library Layout Schematic
XC10: A_CELLS; A_CELLS_M1. arcoc06 is a 100kHz RC oscillator with internal R and C.
axtoc02 *
Crystal Oscillators
X-FAB
1.00 µm
XC10
PT
Analog Library Layout Schematic
XC10: A_CELLS; A_CELLS_M1. axtoc02 is a 1…2MHz crystal oscillator for voltage range from 3.5V to 5.5V.
axtoc03 *
Crystal Oscillators
X-FAB
1.00 µm
XC10
PT
Analog Library Layout Schematic
XC10: A_CELLS; A_CELLS_M1. axtoc03 is a 2…5MHz crystal oscillator for voltage range from 3.5V to 5.5V.
aporc01 *
Power on Reset
X-FAB
1.00 µm
XC10
PT
Analog Library Layout Schematic
XC10: A_CELLS; A_CELLS_M1. aporc01 is a digital power-on-reset circuit. During power-on, POR output is kept high as long as the supply voltage is below the POR threshold voltage. After the threshold has been reached, the POR signals turns low. A delay of
aporc02 *
Power on Reset
X-FAB
1.00 µm
XC10
PT
Analog Library Layout Schematic
XC10: A_CELLS; A_CELLS_M1. aporc02 is a digital power-on-reset circuit. PORB output is kept low as long as the supply voltage is below the POR threshold voltage. PORB signal is generated on both rising and falling edges of the supply voltage. During power
aporc04 *
Power on Reset
X-FAB
1.00 µm
XC10
PT
Analog Library Layout Schematic
XC10: A_CELLS; A_CELLS_M1. aporc04 is a digital power-on-reset circuit. PORB output is kept low as long as the supply voltage is below the high POR threshold voltage. PORB signal is generated on both rising and falling edges of the supply voltage. During
apogc01 *
Power on Reset
X-FAB
1.00 µm
XC10
PT
Analog Library Layout Schematic
XC10: A_CELLS; A_CELLS_M1. apogc01 is a general purpose, power good detector. A power good signal (active high) is generated as long as the supply voltage at the VDDA pin lies within the 4.5V - 5.5V limits. When the supply voltage is beyond the either low
adacc01 *
DAC
X-FAB
1.00 µm
XC10
PT
Analog Library Layout Schematic
XC10: A_CELLS; A_CELLS_M1. adacc01 is a 8-bit digital-to-analog converter (DAC) with a R-2R ladder network. The DAC operates with a single 5V supply and external reference voltage.
adacc02 *
DAC
X-FAB
1.00 µm
XC10
PT
Analog Library Layout Schematic
XC10: A_CELLS; A_CELLS_M1. adacc02 is a 10-bit digital-to-analog converter (DAC) with a R-2R ladder network. The DAC operates with a single 5V supply and external reference voltage.
adacc03 *
DAC
X-FAB
1.00 µm
XC10
PT
Analog Library Layout Schematic
XC10: A_CELLS; A_CELLS_M1. adacc03 is a 8-bit voltage-scaling digital-to-analog converter (DAC). The device can operate at supply and reference voltages down to 3.2V.
aregc01 *
Voltage Regulator
X-FAB
1.00 µm
XC10
PT
Analog Library Layout Schematic
XC10: A_CELLS; A_CELLS_M1. aregc01 is a 5V / 3.3V positive voltage linear regulator for up to 10 mA load current.
aregc02 *
Voltage Regulator
X-FAB
1.00 µm
XC10
PT
Analog Library Layout Schematic
XC10: A_CELLS; A_CELLS_M1. aregc02 is a 2.4V / 3.3V positive voltage switching regulator for on-chip loads and up to 10 mA load current.
adrvc01 *
Driver
X-FAB
1.00 µm
XC10
PT
Analog Library Layout Schematic
XC10: A_CELLS; A_CELLS_M1. adrvc01 is a driver circuit for external loads (relays, LEDs, etc). The circuit features NMOS open-drain output. The rising slope of the output signal can be controlled by means of a bias current.
atmpc01 *
Miscellaneous
X-FAB
1.00 µm
XC10
PT
Analog Library Layout Schematic
XC10: A_CELLS; A_CELLS_M1. atmpc01 is a high-temperature detector. An OVERT output signal (active low) is generated when the chip temperature rises above 140 °C (approx.).
atmpc02 *
Miscellaneous
X-FAB
1.00 µm
XC10
PT
Analog Library Layout Schematic
XC10: A_CELLS; A_CELLS_M1. atmpc02 is a high-temperature detector. An OVERT output signal (active low) is generated when the chip temperature rises above 160 °C (approx.).