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Sel. IP Name Category Provider Geometry Process Name Status Deliverable Description
abiac06_1v8 * Bias
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 1.8V abiac06_1v8 is a general purpose low voltage (down to 1.2V) bias cell. The circuit forces a current of 2µA (approx.) to flow through N-MOS with W/L ratio of 20µm/8µm.

abiac08_1v8 * Bias
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 1.8Vabiac08_1v8 is a general purpose low voltage (down to 1.2V) bias cell. The circuit forces a current of 10µA (approx.) to flow through N-MOS with W/L ratio of 40µm/60µm.

aopac03_1v8 * Operational Amplifier
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 1.8V aopac03_1v8 is a general purpose internally compensated CMOS OpAmp with NMOS native input stage and rail-to-rail output stage. This cell provides typical value of gain bandwidth 1.1MHz and operates with VDD down to 1.2V.

aopac04_1v8 * Operational Amplifier
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 1.8V aopac04_1v8 is a general purpose internally compensated CMOS OpAmp with NMOS native input stage and rail-to-rail output stage. This cell provides typical value of gain bandwidth 3.7MHz and operates with VDD down to 1.2V.

aopac09_1v8 * Operational Amplifier
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 1.8V aopac09_1v8 is a general purpose internally compensated CMOS OpAmp with NMOS native input stage and rail-to-rail output stage. This cell provides typical value of gain bandwidth 162kHz.

aopac10_1v8 * Operational Amplifier
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 1.8V aopac10_1v8 is a general purpose internally compensated CMOS OpAmp with NMOS native input stage and rail-to-rail output stage. This cell provides typical value of gain bandwidth 382kHz.

aopac11_1v8 * Operational Amplifier
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 1.8V aopac11_1v8 is a general purpose internally compensated CMOS OpAmp with NMOS native input stage and rail-to-rail output stage. This cell provides typical value of gain bandwidth 1.5MHz.

aopac12_1v8 * Operational Amplifier
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 1.8V aopac12_1v8 is a general purpose internally compensated CMOS OpAmp with NMOS native input stage and rail-to-rail output stage. This cell provides typical value of gain bandwidth 3.8MHz.

aporc02_1v8 * Power on Reset
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 1.8V aporc02_1v8 is a Power-on-Reset circuit with hysteresis. Both high and low reset signals are available. Reset signals are generated on power-on and power-off transitions. 40mV (typ) hysteresis for safer operation.

aporc03_1v8 * Power on Reset
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 1.8V aporc03_1v8 is a Power-on-Reset circuit with hysteresis. Both high and low reset signals are available. Reset signals are generated on power-on and power-off transitions. 35mV (typ) hysteresis for safer operation.

arcoc01_1v8 * Oscillator
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 1.8V arcoc01_1v8 is a robust 1MHz low-power RC oscillator with internal R and C. The cell features low power consumption. Frequency independent on load capacity.

arcoc02_1v8 * Oscillator
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 1.8V arcoc02_1v8 is a robust 1MHz RC oscillator with internal R and C. Frequency independent on load capacity.

arcoc04_1v8 * Oscillator
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 1.8V arcoc01_1v8 is a robust 5MHz low-power RC oscillator with internal R and C. The cell features low power consumption. Frequency independent on load capacity.

arcoc05-1v8 * Oscillator
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 1.8V arcoc051_1v8 is a robust 5MHz RC oscillator with internal R and C. Frequency independent on load capacity.

arcoc06_1v8 * Oscillator
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 1.8V arcoc06_1v8 is a robust 5MHz low-voltage RC oscillator with internal R and C. The cell operates with VDD down to 1.2V. Frequency independent on load capacity.

arcoc07_1v8 * Oscillator
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 1.8V arcoc07_1v8 is a robust 10MHz RC oscillator with internal R and C. Frequency independent on load capacity.

arcoc08_1v8 * Oscillator
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 1.8V arcoc08_1v8 is a robust 20MHzRC oscillator with internal R and C. Frequency independent on load capacity.

qrcoc09_1v8 * Oscillator
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 1.8V arcoc09_1v8 is a robust 40MHz RC oscillator with internal R and C. Frequency independent on load capacity.

arcoc10_1V8 * Oscillator
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

 XH018 LP3MOS 1.8V arcoc10_1v8 is a robust 100kHz RC oscillator with internal R and C. Frequency independent on load capacity.

arcoc11_1v8 * Oscillator
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 1.8V arcoc11_1v8 is a robust 200kHz RC oscillator with internal R and C. Frequency independent on load capacity.

arcoc12_1v8 * Oscillator
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 1.8V arcoc12_1v8 is a robust 10kHz RC oscillator with internal R and C. Frequency independent on load capacity.

abiac01_3v3 * Bias
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 3.3V abiac01_3v3 is a general purpose bias cell. the circuit provides bias voltages so that a current of 200nA (approx.) to flow through PMOS with W/L ration of 8µm/10µm and NMOS with W/L ratio of 4µm/20µm.

abiac02_3v3 * Bias
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 3.3V abiac02_3v3 is a general purpose bias cell. the circuit provides bias voltages so that a current of 2µA (approx.) to flow through PMOS with W/L ration of 10µm/4µm and NMOS with W/L ratio of 6µm/12µm.

abiac03_3v3 * Bias
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 3.3V abiac03_3v3 is a general purpose bias cell. the circuit provides bias voltages so that a current of 10µA (approx.) to flow through PMOS with W/L ration of 24µm/2µm and NMOS with W/L ratio of 14µm/6µm.

acsoc01_3v3 * Current Source
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 3.3V acsoc01_3v3 is a compact general purpose current source. The circuit has four outputs that drive currents of 200nA each. The current outputs can be connected in parallel in order to obtain bigger output currents in the 200nA-800nA range.

acsoc02_3v3 * Oscillator
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 3.3V acsoc02_3v3 is a compact general purpose current source. The circuit has four outputs that drive currents of 1µA; 2µA; 4µA; and 8µA, respectively.

abgpc01_3v3 * Bandgaps
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 3.3V abgpc01_3v3 is a general purpose bandgap reference with N-well resistors. This bandgap cell also provides reference voltage for some bias cells.

abgpc02_3v3 * Bandgaps
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 3.3V abgpc02_3v3 is a general purpose bandgap reference with polysilicon resistors.

abgpc04_3v3 * Bandgaps
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 3.3V abgpc04_3v3 is a low-voltage bandgap reference with N-well resistors.

aopac01_3v3 * Operational Amplifier
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 3.3V aopac01_3v3 is a general purpose internally compensated CMOS OpAmp with N-MOS input stage and rail-to-rail output stage. The speed, gain bandwidth, and the power consumption of the amplifier are set by means of a bias current.

 

MP = Mass ProductionPT = Prototyping, Silicon provenID = in DesignVS = Verified by Simulations (Soft-IP)

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X-FAB will take no responsibility nor any liability whatsoever for the information or products offered or provided by the other IP suppliers at the database of the Intellectual Partner Network. X-FAB shall have no liability towards the customers for any use of and/or reliance of the products provided by the other IP suppliers at the database of the Intellectual Partner Network.

X-FAB's own IP is subject to a license agreement. X-FAB IP marked with “*” are part of the Master Kit or Master Kit Plus library. If you can not find the IP you are looking for, please contact the respective sales manager in your region. We continuously extend our libraries and offer a custom cell development service as well.