IP Portal

Sel. IP Name Category Provider Geometry Process Name Status Deliverable Description
axtoc04 Crystal Oscillators
X-FAB
0.60 µm
XC06
PT
Layout
Schematic
Analog Library

XC06: A_CELLS.

BGR 0.6u Bandgaps
Ridgetop Group
0.60 µm
XC06
PT
GDSII

Low Power, Wide Supply Range, CMOS

BIAS Bias
X-FAB
0.60 µm
XB06
PT
Verilog
Schematic
Layout
Analog Library

XB06: LNA library: RF_BIAS_CELLS. BIAS is a bias cell intended for use with various RF building blocks. It is designed as a bandgap reference as well as voltage-to-current converter. Current biasing is preferable because of the higher immunity to interfer

BIAS Bias
X-FAB
0.35 μm
XH035
PT
Schematic
Layout
Analog Library

XH035: BIAS Library: RF_BIAS_CELLS. BIAS is a bias cell intended for use with the various RF building blocks. It is based on a bandgap reference and voltage-to-current converters. Current biasing is preferable because of the higher immunity to interferenc

CM1112ae Voltage Regulator
chipus
0.35 μm
XH035
MP
GDSII
Verilog
LVS Netlist

General purpose linear voltage regulator. The circuit generates a 3.3V output voltage from an unregulated input voltage ranging from 5V to 30V. It features short circuit protection and 5mA output current capability.

CM1412ae Power on Reset
chipus
0.35 μm
XH035
MP
GDSII
Verilog
LVS Netlist

2Low consumption Power-On Reset (POR) core. The core has a voltage sense (configurable 0.9V - 5.5V), an internal current bias circuit and two configurable assertion delays (default are > 1μs and > 20μs). A configurable hysteresis (default 100mV).

CM1511ae Other
chipus
0.35 μm
XH035
MP
GDSII
Verilog
LVS Netlist

Low consumption combo voltage and current reference core. The circuit generates an unbuffered 1.29V, temperature compensated voltage reference (70ppm/°C) and provides a 1.6μA PMOS current branch (200ppm/°C).

CM2013ae ADC
chipus
0.35 μm
XH035
PT
GDSII
Verilog
LVS Netlist

Low power, general purpose, 10-bit, 50kSPS, Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) core. The circuit uses one 3.3V analog supply and one 3.3V digital supply and is targeted for microcontroller applications.

CM4013ae Oscillator
chipus
0.35 μm
XH035
MP
GDSII
Verilog
LVS Netlist

General purpose, low power internal oscillator core, 12MHz. The circuit has internal level shifting and start-up circuits. A 4-bit digital bus allows frequency calibration against process variations. Current consumption <40μA, supply voltage 2.7V-3.6V

CM6011ae Other
chipus
0.35 μm
XH035
PT
GDSII
Verilog
LVS Netlist

General purpose capacitive sensor core. The circuit is intended for touch sensing applications for use in microcontrollers and has two multiplexed inputs. 3pF input sensibility and output frequency of 460kHz - 600kHz.

CM6111ae Other
chipus
0.35 μm
XH035
PT
GDSII
Verilog
LVS Netlist

30V/20mA Power Driver/Switch - Two modes of operation: switch or programmable current output; short-circuit protection, over-current detection.

Comparator 0.6u Comparators
Ridgetop Group
0.60 µm
XC06
PT
GDSII

Ultra Low Power, Wide Supply Range, CMOS

DAC-7bit-0.6u DAC
Ridgetop Group
0.60 µm
XC06
PT
GDSII

Low Power, Wide Supply Range, CMOS, output to pos rail

dac10 DAC
X-FAB
0.80 µm
CX08
PT
Schematic
Layout
Analog Library

CX08A: Analog library. DAC10 is a 10-bit digital-to-analog converter. The architecture is based on two resistor dividers. Because of its high output impedance, which is also code dependent, a low offset buffer operational amplifier is strictly recomm

DAC10 DAC
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. DAC10 is a 10-bit digital-to-analog converter. The architecture is based on two resistor dividers. Because of its high output impedance, which is also code dependent, a low offset buffer operational amplifier is strictly recommended at the

DAC6rs DAC
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. DAC6rs is a 6-bit digital-to-analog converter. The architecture is based on a resistor divider. The output impedance is code dependent.

dac8 DAC
X-FAB
0.80 µm
CX08
PT
Schematic
Layout
Analog Library

CX08A: Analog library. DAC8 is a 8-bit digital-to-analog converter. The architecture is based on two resistor dividers. Because of its high output impedance, which is also code dependent, a low offset buffer operational amplifier is strictly recommen

DAC8 DAC
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. DAC8 is a 8-bit digital-to-analog converter. The architecture is based on two resistor dividers. Because of its high output impedance, which is also code dependent, a low offset buffer operational amplifier is strictly recommended at the ou

DAC8rs DAC
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. DAC8rs is a 8-bit digital-to-analog converter. The architecture is based on a resistor divider. The output impedance is code dependent.

DC-DC Converter DC/DC Converters
Ridgetop Group
0.60 µm
XC06
ID
GDSII

Ultra high efficiency programmable output voltage over wide input voltage range, buck/boost. Input: 1.5V - 15V. Output 2V-6V

DIV32 Divider
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: LNA library: RF_DIVIDER_CELLS. DIV32 is a Prescaler with a fixed divider ratio of 32. It should be biased by the RF bias cell.

DIV32 Divider
X-FAB
0.35 μm
XH035
PT
Layout
Schematic
Analog Library

XH035: DIVIDER Library: RF_DIVIDER_CELLS. DIV32 is a Prescaler with a fixed ratio of 32. It should be biased by the RF bias cell.

DPIN Integrated Photodiode
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: OEIC Building Block Library. DPIN_5050 and DPIN_50100 are fast photodiodes with a vertical PIN structure optimized forred light (660nm).

DT2120 ADC
Digian Technology,Inc.
0.35 μm
XH035
MP
GDSII

The dT2120 is designed featuring low-voltage and low-power mono ADC (Analog-to -Digital Converter) for sensor applications. The ADC architecture is using 4th-order 1bit sigma-delta modulator with 64-times oversampling. The dT2120’s in

EnDAT2.2 Soft IP
MAZeT Gmbh
All Geometries
All Processes
VS
VHDL

Sensor Interface used in positioning systems. Visit MAZet website for datasheet.

High V Input Cell Other
Ridgetop Group
0.35 μm
XH035
ID
GDSII

High Voltage Input for input voltages up to 100V

IPMS_16550 Soft IP
Fraunhofer IPMS
All Geometries
All Processes
PT
VHDL
Verilog

The UART-core IPMS_16550 realize the functionality of an serial interface.

Features:

Data rates, data formats and interrupt events are programmable

compatible to UART 16550

high flexibility in different uses

IPMS_16CXX Microprocessor
Soft IP
Fraunhofer IPMS
All Geometries
All Processes
PT
VHDL

8 Bit Microprocessor.

The core IPMS_16CXX realizes a to the PIC 16CXX-family of the firm Microchip compatible 8-bit microcontroller Important features are:

- 8-bit arithmetic (addition, subtraction, logical operations, bit manipulation)

- to 64 k i

IPMS_430 Microprocessor
Soft IP
Fraunhofer IPMS
All Geometries
All Processes
PT
VHDL

16 Bit Microcontroller

The core IPMS_430 is compatible in its properties, like instruction set, address space and time behavior with the standard CPU MSP430 from TI. Important features are

- 16 bit Risc CPU

- 7 address modes for source operands

- 4 a

IPMS_AES Soft IP
Fraunhofer IPMS
All Geometries
All Processes
VS
VHDL
Verilog

Cryptographie core according to AES standard

Features

High processing speed of 100 Mbit / s (128 bit key, 25 MHz).

Same speed for coding and decoding.

Key widths of 128, 192 and 256 bit are implemented

120 kGates.

 

MP = Mass ProductionPT = Prototyping, Silicon provenID = in DesignVS = Verified by Simulations (Soft-IP)

Displaying results 301 to 330 out of 370

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