IP Portal

Sel. IP Name Category Provider Geometry Process Name Status Deliverable Description
aopac03_5v Operational Amplifier
X-FAB
0.18 μm
XC018
PT
Analog Library
Layout
Schematic

XC018 LP 5V aopac03_5v is a general purpose internally compensated CMOS OpAmp with N-MOS input and rail-to-rail output stage.

aopac03_5v Operational Amplifier
X-FAB
0.18 μm
XC018
PT
Analog Library
Layout
Schematic

XC018 LP 5V aopac03_5v is a general purpose internally compensated CMOS OpAmp with P-MOS input stage and rail-to-rail output stage.

acmpc03_5v Comparators
X-FAB
0.18 μm
XC018
PT
Analog Library
Layout
Schematic

XC018 LP 5V acmpc03_5v is a rail-to-rail input, current-programmable CMOS comparator.

axtoc01_5v Crystal Oscillators
X-FAB
0.18 μm
XC018
PT
Analog Library
Layout
Schematic

XC018 LP 5V axtoc01_5v is a robust 32.7689 kHz crystal oscillator for supply voltage range from 3.5V to 5.5V.

axtoc02_5v Crystal Oscillators
X-FAB
0.18 μm
XC018
PT
Analog Library
Layout
Schematic

XC018 LP 5V axtoc02-5v is a robust 1-4 MHz crystal oscillator for supply voltage range from 3.5V to 5.5V.

aadcc01_5v ADC
X-FAB
0.18 μm
XC018
PT
Analog Library
Layout
Schematic

XC018 LP 5V aadcc01_5v is a 10-bit successive approximation Analog-to-Digital converter (ADC). The ADC operated with a single 5.0V analog power supply, 1.8V digital power supply and an external voltage reference.

adacc01_5v ADC
X-FAB
0.18 μm
XC018
PT
Analog Library
Layout
Schematic

XC018 LP 5V is a 10-bit voltage -scaling (potentiometric) digital-to-analog converter (DAC). The DAC operates with a single 5.0V analog power supply, a 1.8V digital power supply and external reference voltage.

aporc03_5v Power on Reset
X-FAB
0.18 μm
XC018
PT
Analog Library
Layout
Schematic

XC018 LP 5V aporc03_5v is a power-on-Reset circuit. Reset signals are generated on both the rising and falling edge of the supply voltage.

atmpc01_5v Other
X-FAB
0.18 μm
XC018
PT
Analog Library
Layout
Schematic

XC018 LP 5V atmpc01_5v is an over-temperature detector. When the chip temperature rises over the high threshold temperature (~125°C) the output signal turns high.

CM2013ae ADC
chipus
0.35 μm
XH035
PT
GDSII
Verilog
LVS Netlist

Low power, general purpose, 10-bit, 50kSPS, Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) core. The circuit uses one 3.3V analog supply and one 3.3V digital supply and is targeted for microcontroller applications.

CM6011ae Other
chipus
0.35 μm
XH035
PT
GDSII
Verilog
LVS Netlist

General purpose capacitive sensor core. The circuit is intended for touch sensing applications for use in microcontrollers and has two multiplexed inputs. 3pF input sensibility and output frequency of 460kHz - 600kHz.

CM6111ae Other
chipus
0.35 μm
XH035
PT
GDSII
Verilog
LVS Netlist

30V/20mA Power Driver/Switch - Two modes of operation: switch or programmable current output; short-circuit protection, over-current detection.

DAC-7bit-0.6u DAC
Ridgetop Group
0.60 µm
XC06
PT
GDSII

Low Power, Wide Supply Range, CMOS, output to pos rail

Comparator 0.6u Comparators
Ridgetop Group
0.60 µm
XC06
PT
GDSII

Ultra Low Power, Wide Supply Range, CMOS

abiac06_1v8 Bias
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 1.8V abiac06_1v8 is a general purpose low voltage (down to 1.2V) bias cell. The circuit forces a current of 2µA (approx.) to flow through N-MOS with W/L ratio of 20µm/8µm.

BGR 0.6u Bandgaps
Ridgetop Group
0.60 µm
XC06
PT
GDSII

Low Power, Wide Supply Range, CMOS

abgpc05_1v8 Bandgaps
X-FAB
0.18 μm
XH018
PT
Layout
Schematic
Analog Library

XH018 LP3MOS 1.8V abgpc05_1v8 is a general purpose 1.2V bandgap reference with N-well resistors and NPN (qnva) diode matrix.

abgpc01_1v8 Bandgaps
X-FAB
0.18 μm
XH018
PT
Layout
Schematic
Analog Library

 XH018 LP3MOS 1.8V abgpc01_1v8 is a general purpose 1.2V bandgap reference with N-well resistirs and PNP (qpvc) diode matrix

abiac08_1v8 Bias
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 1.8Vabiac08_1v8 is a general purpose low voltage (down to 1.2V) bias cell. The circuit forces a current of 10µA (approx.) to flow through N-MOS with W/L ratio of 40µm/60µm.

aopac03_1v8 Operational Amplifier
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 1.8V aopac03_1v8 is a general purpose internally compensated CMOS OpAmp with NMOS native input stage and rail-to-rail output stage. This cell provides typical value of gain bandwidth 1.1MHz and operates with VDD down to 1.2V.

aopac04_1v8 Operational Amplifier
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 1.8V aopac04_1v8 is a general purpose internally compensated CMOS OpAmp with NMOS native input stage and rail-to-rail output stage. This cell provides typical value of gain bandwidth 3.7MHz and operates with VDD down to 1.2V.

aopac09_1v8 Operational Amplifier
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 1.8V aopac09_1v8 is a general purpose internally compensated CMOS OpAmp with NMOS native input stage and rail-to-rail output stage. This cell provides typical value of gain bandwidth 162kHz.

aopac10_1v8 Operational Amplifier
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 1.8V aopac10_1v8 is a general purpose internally compensated CMOS OpAmp with NMOS native input stage and rail-to-rail output stage. This cell provides typical value of gain bandwidth 382kHz.

aopac11_1v8 Operational Amplifier
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 1.8V aopac11_1v8 is a general purpose internally compensated CMOS OpAmp with NMOS native input stage and rail-to-rail output stage. This cell provides typical value of gain bandwidth 1.5MHz.

aopac12_1v8 Operational Amplifier
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 1.8V aopac12_1v8 is a general purpose internally compensated CMOS OpAmp with NMOS native input stage and rail-to-rail output stage. This cell provides typical value of gain bandwidth 3.8MHz.

aporc02_1v8 Power on Reset
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 1.8V aporc02_1v8 is a Power-on-Reset circuit with hysteresis. Both high and low reset signals are available. Reset signals are generated on power-on and power-off transitions. 40mV (typ) hysteresis for safer operation.

aporc03_1v8 Power on Reset
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 1.8V aporc03_1v8 is a Power-on-Reset circuit with hysteresis. Both high and low reset signals are available. Reset signals are generated on power-on and power-off transitions. 35mV (typ) hysteresis for safer operation.

arcoc01_1v8 Oscillator
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 1.8V arcoc01_1v8 is a robust 1MHz low-power RC oscillator with internal R and C. The cell features low power consumption. Frequency independent on load capacity.

arcoc02_1v8 Oscillator
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 1.8V arcoc02_1v8 is a robust 1MHz RC oscillator with internal R and C. Frequency independent on load capacity.

arcoc04_1v8 Oscillator
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 1.8V arcoc01_1v8 is a robust 5MHz low-power RC oscillator with internal R and C. The cell features low power consumption. Frequency independent on load capacity.

 

MP = Mass ProductionPT = Prototyping, Silicon provenID = in DesignVS = Verified by Simulations (Soft-IP)

Displaying results 301 to 330 out of 370

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