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Sel. IP Name Category Provider Geometry Process Name Status Deliverable Description
aporc03 Power on Reset
X-FAB
0.60 µm
XC06
PT
Layout
Schematic
Analog Library

XC06: A_CELLS. aporc03 is a Power-on-Reset circuit. Reset signals are generated on both the rising and falling edge of the supply voltage. During power-on, POR output is kept low as long as the supply voltage is bellow the threshold voltage. When the high

aporc01 Power on Reset
X-FAB
0.35 μm
XH035
PT
Layout
Schematic
Analog Library

XH035: A_CELLS. For MOS module only. aporc01 is a dynamic Power-on-Reset circuit. During power-on, POR output follows the supply voltage as long as it is below the threshold voltage. When the threshold voltage is reached, the POR signal turns low. A delay

aporc02 Power on Reset
X-FAB
0.35 μm
XH035
PT
Layout
Schematic
Analog Library

XH035: A_CELLS. For MOS module only. aporc02 is a Power-on-Reset circuit with hysteresis. Reset signals are generated on both the rising and falling edge of the supply voltage. During power-on, POR output follows the supply voltage as long as it is b

aporc03 Power on Reset
X-FAB
0.35 μm
XH035
PT
Layout
Schematic
Analog Library

XH035: A_CELLS. For MOS module only. aporc03 is a Power-on-Reset circuit. Reset signals are generated on both the rising and falling edge of the supply voltage. During power-on, POR output follows the supply voltage as long as it is below the threshold v

aporc01_5v Power on Reset
X-FAB
0.18 μm
XC018
PT
Layout
Schematic
Analog Library

XC018 LP 5V aporc01_5v is a dynamic Power-on-Reset (POR) circuit. During power-on, POR output follows the supply voltage as long as it is below the threshold voltage. When the threshold voltage is reached, the POR signal turns low.

aporc02_5v Power on Reset
X-FAB
0.18 μm
XC018
PT
Layout
Schematic
Analog Library

XC018 LP 5V aporc02_5v is a Power-on-Reset (POR) circuit with hysteresis. Reset signals are generated on both the rising and falling edge of the supply voltage.

aporc03_5v Power on Reset
X-FAB
0.18 μm
XC018
PT
Layout
Schematic
Analog Library

XC018 LP 5V aporc03_5v is a Power-on-Reset (POR) circuit. Reset signals are generated on both the rising and falling edge of the supply voltage.

aporc01 Power on Reset
X-FAB
0.60 µm
XT06
PT
Layout
Schematic
Analog Library

XT06 aporc01 is a dynamic Power-on-Reset circuit. During power-on, POR output is kept high as long as the supply voltage is below the POR threshold voltage. When the threshold voltage is reached, the POR signal turns low.

aporc02 Power on Reset
X-FAB
0.60 µm
XT06
PT
Layout
Schematic
Analog Library

XT06 aporc02 is a Power-on-Reset circuit with hysteresis. Reset signal are generated on both the rising and failing edge of the supply voltage. During power-on, POR outputs is kept high as long as the supply voltage is below the threshold voltage.

aporc03 Power on Reset
X-FAB
0.60 µm
XT06
Layout
Schematic
Analog Library

XT06 aporc03 is a Power-on-Rest circuit. Reset signals are generated on both the rising and falling edge of the supply voltage. During power-on, POR output is kept high as long as the supply voltage is below the high threshold.

QCPOR4_35X Power on Reset
QualCore Logic, Inc.
0.35 μm
XH035
MP
GDSII
Schematic

Power On Reset cell

aporc01_3v3 Power on Reset
X-FAB
0.18 μm
XC018
PT
Layout
Schematic
Analog Library

XC018 LP 3.3V aporc01_3v3 is a dynamic power-on-reset circuit (POR). The cell is suitable for applicaitons where low consumption is important.

aporc02_3v3 Power on Reset
X-FAB
0.18 μm
XC018
PT
Layout
Schematic
Analog Library

XC018 LP 3.3V aporc02_3v3 is a Power-on-Reset circuit with hysteresis. Reset signals are generated on both the rising and falling edge of the supply voltage.

aporc03_3v3 Power on Reset
X-FAB
0.18 μm
XC018
PT
Layout
Schematic
Analog Library

XC018 LP 3.3V aporc03_3v3 is a Power-on-Rest circuit. Reset signals are generated on both the rising and falling edge of the supply voltage.

aporc03_5v Power on Reset
X-FAB
0.18 μm
XC018
PT
Analog Library
Layout
Schematic

XC018 LP 5V aporc03_5v is a power-on-Reset circuit. Reset signals are generated on both the rising and falling edge of the supply voltage.

CM1412ae Power on Reset
chipus
0.35 μm
XH035
MP
GDSII
Verilog
LVS Netlist

2Low consumption Power-On Reset (POR) core. The core has a voltage sense (configurable 0.9V - 5.5V), an internal current bias circuit and two configurable assertion delays (default are > 1μs and > 20μs). A configurable hysteresis (default 100mV).

aporc02_1v8 Power on Reset
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 1.8V aporc02_1v8 is a Power-on-Reset circuit with hysteresis. Both high and low reset signals are available. Reset signals are generated on power-on and power-off transitions. 40mV (typ) hysteresis for safer operation.

aporc03_1v8 Power on Reset
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 1.8V aporc03_1v8 is a Power-on-Reset circuit with hysteresis. Both high and low reset signals are available. Reset signals are generated on power-on and power-off transitions. 35mV (typ) hysteresis for safer operation.

aporc02_3v3 Power on Reset
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 3.3V aporc02_3v3 is a Power-on-Reset circuit with hysteresis. Reset signal are generated on power-on and power-off transitions. Both high and low (POR and PORB) reset signals are available.

aporc03_3v3 Power on Reset
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 3.3V aporc02_3v3 is a Power-on-Reset circuit. Reset signal are generated on power-on and power-off transitions. Both high and low (POR and PORB) reset signals are available.

PA Power Amplifiers
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: LNA library: RF_PA_CELLS. PA is a non-linear Power Amplifier that is intended for the transmission of ASK and FSK signals. Its output power level can be digitally controlled in 4 steps. It should be biased by the RF bias cell.

SA00PFC000 PLL
Sony LSI Design Inc.
0.35 μm
XH035
ID
GDSII

SA00PFC000 is a PLL with internal loop filter. Wide output clock freq. range : 10MHz~200MHz. Wide input clock freq. range : 2MHz~50MHz

SA00PFC010 PLL
Sony LSI Design Inc.
0.35 μm
XH035
ID
GDSII

SA00PFC010 is a PLL with internal loop filter. Wide output clock freq. range : 10MHz~160MHz. Wide input clock freq. range : 2.5MHz~6MHz.

QCADB5_35X Other
QualCore Logic, Inc.
0.35 μm
XH035
PT
GDSII
Schematic

Connectivity IP. This is a product chip.

MR74039 Other
Moortec Semiconductor Ltd
0.35 μm
XH035
ID
GDSII
Verilog

The MR74039 is a fully integrated temperature sensor with a 12 Bit digital output designed in the XFab 0.35um XH035 process. It utilises a 12 bit Sigma Delta ADC for increased precision (0.25ºC). The temperature measurement range is fr

AR25X01 Other
Archband Labs Inc.
0.25 μm
FC025
PT
GDSII

AR25X01 is a 35mA LDO with the capless option in 0.25µm node

Low Power DDS Other
Saul Research
0.35 μm
XH035
PT
GDSII
Schematic

Novel aproach to Direct Digital Synthesis, using a voltage-ladder reference. Accuracy is achieved by using a full resistor ladder array, so bit size equivalent to 12 bits has been shown. Prototypes using an 8 bit system are available on

Analogue SSB Chip Other
Saul Research
0.35 μm
XH035
PT
GDSII
Schematic

Very low power (3V, 25uA) 90 degree analogue phase shifter for SSB encoding/decoding. A full description is on the web site, with all measurements.

IPMS_DES Other
Soft IP
Fraunhofer IPMS
All Geometries
All Processes
VS
VHDL
Verilog

Cryptographic Processor Core for the DES Algorithm

The hardware realizes a flexible DES core to encrypt and decrypt data with high speed. The encryption /decryption of a 64 bit data set takes 16 clock periods.

IPMS_IIC Other
Soft IP
Fraunhofer IPMS
All Geometries
All Processes
PT
VHDL
Verilog

The core realized the I²C-bus protocol

Features:

Master and receive mode realized

Bus node address and data transmission rate are programmable

8 Bit data interface to the controller

All I²C function are implemented

Core is multimasterable   

 

MP = Mass ProductionPT = Prototyping, Silicon provenID = in DesignVS = Verified by Simulations (Soft-IP)

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