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XC06: A_CELLS. aporc01 is a dynamic Power-on-Reset circuit. During power-on, POR output is kept high as long as the supply voltage is bellow the POR threshold voltage. When the threshold voltage is reached, the POR signal turns low. A delay of few microse

XC06: A_CELLS. aporc02 is a Power-on-Reset circuit with hysteresis. Reset signals are generated on both the rising and falling edge of the supply voltage. During power-on, POR output is kept high as long as the supply voltage is bellow the high threshold

XC06: A_CELLS. aporc03 is a Power-on-Reset circuit. Reset signals are generated on both the rising and falling edge of the supply voltage. During power-on, POR output is kept low as long as the supply voltage is bellow the threshold voltage. When the high

XH035: A_CELLS. For MOS module only. aporc01 is a dynamic Power-on-Reset circuit. During power-on, POR output follows the supply voltage as long as it is below the threshold voltage. When the threshold voltage is reached, the POR signal turns low. A delay

XH035: A_CELLS. For MOS module only. aporc02 is a Power-on-Reset circuit with hysteresis. Reset signals are generated on both the rising and falling edge of the supply voltage. During power-on, POR output follows the supply voltage as long as it is b

XH035: A_CELLS. For MOS module only. aporc03 is a Power-on-Reset circuit. Reset signals are generated on both the rising and falling edge of the supply voltage. During power-on, POR output follows the supply voltage as long as it is below the threshold v

XC018 LP 5V aporc01_5v is a dynamic Power-on-Reset (POR) circuit. During power-on, POR output follows the supply voltage as long as it is below the threshold voltage. When the threshold voltage is reached, the POR signal turns low.

XC018 LP 5V aporc02_5v is a Power-on-Reset (POR) circuit with hysteresis. Reset signals are generated on both the rising and falling edge of the supply voltage.

XC018 LP 5V aporc03_5v is a Power-on-Reset (POR) circuit. Reset signals are generated on both the rising and falling edge of the supply voltage.

XT06 aporc01 is a dynamic Power-on-Reset circuit. During power-on, POR output is kept high as long as the supply voltage is below the POR threshold voltage. When the threshold voltage is reached, the POR signal turns low.

XT06 aporc02 is a Power-on-Reset circuit with hysteresis. Reset signal are generated on both the rising and failing edge of the supply voltage. During power-on, POR outputs is kept high as long as the supply voltage is below the threshold voltage.

XT06 aporc03 is a Power-on-Rest circuit. Reset signals are generated on both the rising and falling edge of the supply voltage. During power-on, POR output is kept high as long as the supply voltage is below the high threshold.

Power On Reset cell

XC018 LP 3.3V aporc01_3v3 is a dynamic power-on-reset circuit (POR). The cell is suitable for applicaitons where low consumption is important.

XC018 LP 3.3V aporc02_3v3 is a Power-on-Reset circuit with hysteresis. Reset signals are generated on both the rising and falling edge of the supply voltage.

XC018 LP 3.3V aporc03_3v3 is a Power-on-Rest circuit. Reset signals are generated on both the rising and falling edge of the supply voltage.

XC018 LP 5V aporc03_5v is a power-on-Reset circuit. Reset signals are generated on both the rising and falling edge of the supply voltage.

2Low consumption Power-On Reset (POR) core. The core has a voltage sense (configurable 0.9V - 5.5V), an internal current bias circuit and two configurable assertion delays (default are > 1μs and > 20μs). A configurable hysteresis (default 100mV).

XB06: LNA library: RF_PA_CELLS. PA is a non-linear Power Amplifier that is intended for the transmission of ASK and FSK signals. Its output power level can be digitally controlled in 4 steps. It should be biased by the RF bias cell.

SA00PFC000 is a PLL with internal loop filter. Wide output clock freq. range : 10MHz～200MHz. Wide input clock freq. range : 2MHz～50MHz

SA00PFC010 is a PLL with internal loop filter. Wide output clock freq. range : 10MHz～160MHz. Wide input clock freq. range : 2.5MHz～6MHz.

Connectivity IP. This is a product chip.

The MR74039 is a fully integrated temperature sensor with a 12 Bit digital output designed in the XFab 0.35um XH035 process. It utilises a 12 bit Sigma Delta ADC for increased precision (0.25ºC). The temperature measurement range is fr

AR25X01 is a 35mA LDO with the capless option in 0.25µm node

Novel aproach to Direct Digital Synthesis, using a voltage-ladder reference. Accuracy is achieved by using a full resistor ladder array, so bit size equivalent to 12 bits has been shown. Prototypes using an 8 bit system are available on

Very low power (3V, 25uA) 90 degree analogue phase shifter for SSB encoding/decoding. A full description is on the web site, with all measurements.

Cryptographic Processor Core for the DES Algorithm

The hardware realizes a flexible DES core to encrypt and decrypt data with high speed. The encryption /decryption of a 64 bit data set takes 16 clock periods.

The core realized the I²C-bus protocol

Features:

Master and receive mode realized

Bus node address and data transmission rate are programmable

8 Bit data interface to the controller

All I²C function are implemented

Core is multimasterable   

XC018 LP 3.3V atmpc01_3v3 is an over-temperature detector. When the chip temperature rises over the high threshold temperature (~130°C) the output signal turns high.

XC018 LP 5V atmpc01_5v is an over-temperature detector. When the chip temperature rises over the high threshold temperature (~125°C) the output signal turns high.