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IP Name	Category	Provider	Geometry	Process Name	Status	Deliverable	Description
ADC12DR	ADC	A3PICs GmbH	0.60 µm	XB06	PT	GDSII	The ADC12DR is a SAR-based low-power ADC with a 12bit resolution. Its fully differential input stage features a rail-to-rail input range. At a sampling rate of 2MS/s a power consumption of only 10mW is attained applying a 5V power suppl
AV2102 600mA Buck	Voltage Regulator	Aivaka	0.60 µm	XC06	PT	GDSII	DC/DC regulator.
AV2110 600mA Buck	Voltage Regulator	Aivaka	0.60 µm	XC06	PT	GDSII	DC/DC Buck Regulator with 0% to 100% duty cycle.
AR32X3A	ADC	Archband Labs Inc.	0.25 μm	FC025	PT	GDSII	AR32X3A is a 16-bit ADC for measurement purpose in 0.25µm node.
AR25X01	Other	Archband Labs Inc.	0.25 μm	FC025	PT	GDSII	AR25X01 is a 35mA LDO with the capless option in 0.25µm node
DT2120	ADC	Digian Technology,Inc.	0.35 μm	XH035	MP	GDSII	The dT2120 is designed featuring low-voltage and low-power mono ADC (Analog-to -Digital Converter) for sensor applications. The ADC architecture is using 4th-order 1bit sigma-delta modulator with 64-times oversampling. The dT2120’s in
IPMS_430	Microprocessor Soft IP	Fraunhofer IPMS	All Geometries	All Processes	PT	VHDL	16 Bit Microcontroller The core IPMS_430 is compatible in its properties, like instruction set, address space and time behavior with the standard CPU MSP430 from TI. Important features are - 16 bit Risc CPU - 7 address modes for source operands - 4 a
IPMS_16CXX	Microprocessor Soft IP	Fraunhofer IPMS	All Geometries	All Processes	PT	VHDL	8 Bit Microprocessor. The core IPMS_16CXX realizes a to the PIC 16CXX-family of the firm Microchip compatible 8-bit microcontroller Important features are: - 8-bit arithmetic (addition, subtraction, logical operations, bit manipulation) - to 64 k i
IPMS_16550	Soft IP	Fraunhofer IPMS	All Geometries	All Processes	PT	VHDL Verilog	The UART-core IPMS_16550 realize the functionality of an serial interface. Features: Data rates, data formats and interrupt events are programmable compatible to UART 16550 high flexibility in different uses
IPMS_AES	Soft IP	Fraunhofer IPMS	All Geometries	All Processes	VS	VHDL Verilog	Cryptographie core according to AES standard Features High processing speed of 100 Mbit / s (128 bit key, 25 MHz). Same speed for coding and decoding. Key widths of 128, 192 and 256 bit are implemented 120 kGates.
IPMS_CAN	Soft IP	Fraunhofer IPMS	All Geometries	All Processes	PT	VHDL Verilog	CAN-Controller Features implementation of the Basic CAN specification no generated Overload Frames receiving and transmitting of both identifiers (CAN specification 2.0B) programmable data rate up to 1 Mbit/s programmable
IPMS_DES	Other Soft IP	Fraunhofer IPMS	All Geometries	All Processes	VS	VHDL Verilog	Cryptographic Processor Core for the DES Algorithm The hardware realizes a flexible DES core to encrypt and decrypt data with high speed. The encryption /decryption of a 64 bit data set takes 16 clock periods.
IPMS_ECC	Soft IP	Fraunhofer IPMS	All Geometries	All Processes	VS	VHDL Verilog	Processor core for Elliptic Curve Cryptography IEEE-Standard 1076-1993 compliant synthesizable VHDL model for utiliza¬tion as macro cell in ASIC and FPGA designs Diffie-Hellman key exchange proto¬col exists Implementation of other proto¬cols based o
IPMS_IIC	Other Soft IP	Fraunhofer IPMS	All Geometries	All Processes	PT	VHDL Verilog	The core realized the I²C-bus protocol Features: Master and receive mode realized Bus node address and data transmission rate are programmable 8 Bit data interface to the controller All I²C function are implemented Core is multimasterable
IPMS_IRHSP	Soft IP	Fraunhofer IPMS	All Geometries	All Processes	VS	VHDL	IrDA Hight Speed Protocl Stack Features: Complete IrDA protocol stack (IrPHY, Framer, IrLAP, IrLMP, IAS, TinyTP, IrCOMM, IrOBEX) Primary and secondary function (scalable) Data rates from 9.6 kbit / s - 16 Mbit / s (scalable) IR remote control functio
IPMS_LIN	Soft IP	Fraunhofer IPMS	All Geometries	All Processes	PT	VHDL Verilog	LIN (Local Interconnect Network) is a serial communication protocol Features Support of LIN specification 2.0 Programmable data rate between 1 Kbit/s and 20 Kbit/s 4 MHz clock frequency 8-byte data buffer 8-bit host controller interface Support of
IPMS_RSA	Soft IP	Fraunhofer IPMS	All Geometries	All Processes	VS	Verilog VHDL	Cryptographic Processor Core for Public Key En¬cryption processor core for modulo n multiplication and exponentiation (RSA) with high speed and high bit sizes Data rates (for a 1024 bit system at 25 MHz clock frequency) 1024 bit RSA up to 10 kbit/s
HT_ADC1	ADC	IMMS gGmb	1.00 µm	XI10	PT	GDSII Schematic	This IP is a cyclic ADC based on RSD algorithm usable as core for embedded applications. The special advantage of this type of ADC is the reduced complexity of hardware resp. layout area because of the reuse of the main stages for each bit. Up to 13 bit o
EnDAT2.2	Soft IP	MAZeT Gmbh	All Geometries	XC018 XA035 XC06 XB06 CX06 CX08 XC10 XH018	VS	VHDL	Sensor Interface used in positioning systems. Visit MAZet website for datasheet.
SUPI4	Soft IP	MAZeT Gmbh	All Geometries	All Processes	VS	VHDL	Interbus Slave Controller Version 4. Visit MAZeT website for datasheet.
MR74039	Other	Moortec Semiconductor Ltd	0.35 μm	XH035	ID	GDSII Verilog	The MR74039 is a fully integrated temperature sensor with a 12 Bit digital output designed in the XFab 0.35um XH035 process. It utilises a 12 bit Sigma Delta ADC for increased precision (0.25ºC). The temperature measurement range is fr
QCBGB10_35X	Voltage Regulator Bias	QualCore Logic, Inc.	0.35 μm	XH035	MP	GDSII Schematic	Bandgap Voltage Reference and Current Bias Cell.
QCBIAS1_35X	Current Reference Bias	QualCore Logic, Inc.	0.35 μm	XH035	MP	GDSII Schematic	Current Reference and Current Biasing Cell.
QCCMP4_35X	Comparators	QualCore Logic, Inc.	0.35 μm	XH035	MP	GDSII Schematic	Comparator Cell with N-Channel Inputs
QCDAC4_35X	DAC	QualCore Logic, Inc.	0.35 μm	XH035	MP	GDSII Schematic	Resistive String architecture.
QCOP4_35X	Operational Amplifier	QualCore Logic, Inc.	0.35 μm	XH035	MP	GDSII Schematic	Operational Amplifier Cell with P-Channel Inputs
QCOP5_35X	Operational Amplifier	QualCore Logic, Inc.	0.35 μm	XH035	MP	GDSII Schematic	Reference Amplifier
QCPOR4_35X	Power on Reset	QualCore Logic, Inc.	0.35 μm	XH035	MP	GDSII Schematic	Power On Reset cell
QCADB5_35X	Other	QualCore Logic, Inc.	0.35 μm	XH035	PT	GDSII Schematic	Connectivity IP. This is a product chip.
Sub 1dB LNA+mixer	LNA Mixer	Saul Research	0.35 μm	XH035	PT	GDSII Schematic	LNA and optional mixer based on XH035 process. Measured noise figure below 1dB including mixer. Described in a paper on the web site. The techniques are readily applied to other processes.

MP = Mass Production; PT = Prototyping, Silicon proven; ID = in Design; VS = Verified by Simulations (Soft-IP)

Displaying results 1 to 30 out of 318

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The Intellectual Partner Network is a web database provided by X-FAB in cooperation with selected partners. Both X-FAB and a variety of different IP supplier offer their IP to customers using X-FAB’s foundry process. X-FAB will support customers to get in direct contact with the relevant IP supplier.

X-FAB will take no responsibility nor any liability whatsoever for the information or products offered or provided by the other IP suppliers at the database of the Intellectual Partner Network. X-FAB shall have no liability towards the customers for any use of and/or reliance of the products provided by the other IP suppliers at the database of the Intellectual Partner Network.

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