150 entries
Published: July 2010

A novel 0.18μm 200V integrated technology based on Partial SOI and lateral Super Junctions devices is presented. The dielectric isolation inherent in SOI allows simple and areaefficient integration of electrically floating CMOS and HV devices while removing all substrate carrier injection-related parasitic effects. The Super Junctions give a competitively low on-resistance of HVMOS and provide a wide-range breakdown voltage-scaling capability.


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Published: April 2010

An experiment in base and pedestal collector implant has been conducted to study the impact and further improve the performance of a 0.6 micron silicon poly emitter bipolar transistor. It has been shown the bandwidth can be improved form 13GHz to 15GHz with acceptable changes to the other bipolar performances.


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Published: April 2010

The high voltage device can be embedded into conventional shallow trench isolation (STI) logic process. Basically, SVX (Smart Voltage Extension) technique was applied in order to integrate 32V high voltage LDMOS into a standard 0.18 micron low voltage CMOS technology without any process change. However, a double hump issue was being observed in high voltage LDNMOS. The double hump phenomenon is mainly occurs due to lower threshold voltage of transistor corner that will lead to high sub-threshold leakage. This paper presents a solution by applying boron implant in HV LDNMOS to suppress the double hump issue. The retrograde baseline CMOS p-well implant is used for this purpose to avoid an additional mask and process step.


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Published: March 2010

Sub-wavelength structures in metal films have interesting optical properties that can be implemented for sensing applications: gratings act as wire grid polarizer, hole arrays with enhanced transmission can be used as spectral filters. This paper demonstrates the feasibility of these nanostructures using 180 nm and 90 nm complementary metal-oxide semiconductor (CMOS) processes. The metal layers of the process can be used for optical nanostructures with feature sizes down to 100 nm.


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Published: March 2010

For the first time, this paper demonstrates the experimental results for two types of test structures of field transistors up to 200°C. The field transistor structures which are stripe (conventional) and square ring (new) structures were measured and investigated in term of field leakage current and onstate characterization at high temperature.


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Published: October 2009

In this paper we describe a novel tool for modeling the fabrication of MEMS and semiconductor devices, and show some examples of its application in the MEMS foundry business. The tool allows an accurate visualization of the step-by-step crreation of the final 3-D device geometry by using the 2-D layout and a description of the fabrication process.


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Published: August 2009

Monolithically integrated photodiodes with high spectral responsivity over the entire visible and the near infrared spectral range are of growing interest for the semiconductor industry, since the next generation of optical data storage devices (Blue DVD) will soon be brought to market. In this paper, the bandwidth of photodiode dependence on the junction implant conditions and thermal budget was simulated by TCAD. It shows significant dependence on these process conditions. The corresponding mechanism related to RC delay, relationship between depletion region and light absorption will be discussed in detail with the help of simulation pictures and simple model explanation.


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Published: August 2009

In SOC (System on Chip) technology, the various types of devices located on an IC chip typically have different operating voltages thus requiring multiple gate oxide layers of different thickness to be formed. In order to form different gate oxide, several oxide removal and growth steps have to be carried out which make the process more complex and particularly have a detrimental impact on the Shallow Trench Isolation (STI) structures.


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Published: August 2009

This study was carried out to investigate the bimodal distribution of Vt (threshold voltage) of 3.3V differential pair PMOS structure within a wafer in which the abnormal transistor shows half lower than normal threshold voltage value and higher off state leakage current. The root cause was identified by simulation which is increasing gate oxide thickness of thin gate oxide area and finally matches behavior of the abnormal transistor with low threshold voltage and high off state leakage. The solution was implemented with O2 descum process into the dual gate oxide process flow, which O2 descum process was inserted after photo resist patterning for thick gate oxide in order to remove potential thin photo resist scum which is blocking wet etch reaction to oxide and causes thick gate oxide to remain at the thin gate oxide area. Details evaluation, measurement and result will be further discussed.


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Published: August 2009

Resistance of contacts on nonsalicided active must be sufficiently low in order for a device to function. The objective of the work presented here is to discuss steps taken to reduce initially high contact resistance on non-salicided active of a high breakdown voltage transistor to meet functional requirement. In order to create a special 30V high voltage transistor in a NAND flash device, the active region between gate and junction has to be non-salicided. Therefore, the contact resistance needs to be lowered down by other means. This paper shows substantially reduction in contact resistance value and better resistance distribution uniformity across a wafer through a combination of plug implant and improved contact etching with O2 flush condition and additional oxide etching.


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