150 entries
Published: April 2013

In this paper a modified MEMS foundry process allowing the production of 3D inertial sensors, such as accelerometers, gyroscopes and combinations, is introduced. The new MEMS process is suitable for a wide range of applications that use 3D accelerometers or gyroscopes. One-axis and three-axis designs can be produced with the same process, and the fabrication of complex inertial measurement units, in particular, the assembly process, is simplified.


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Published: May 2013

The filters are constituted by a Fabry-Perot resonator formed by two Bragg mirrors separated by a patterned cavity. The filter response can be tuned by changing the geometric parameters of the patterning, and consequently the cavity effective refractive index. In this way, many different filters can be produced at once on a single chip, allowing multichanneling. The filter has been designed, produced, and characterized. The results for a chip with 24 filters are presented.


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Published: May 2013

This paper presents versatile HV lateral JFET design method on 0.18μm SOI BCD technology to achieve variable Vth(pinch-off voltage) and Idsat, without DIBL effect over full operating Vds range and scalable breakdown voltage capability on both N-ch and P-ch JFET. The significant advantage of a HV JFET compared to depletion MOSFET is the lower area consumption in real circuit design which due to higher Idsat values at Vgs=0V.


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Published: December 2012

The fabrication of semiconductor devices, even in the area of customer oriented business, is one of the most complex production tasks in the world. A typical wafer production process consists of several hundred steps with numerous resources like equipments and operating staff. The optimal assignment of each resource at each time for a certain number of wafers is vital for a efficient production process. Several demands defined by the customers and facility management must be taken into consideration with the objective to find the best tradeoff between the different needs.


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Published: December 2012

This paper evaluates the technique used to improve the latching characteristics of the 200V n-type superjunction (SJ) LIGBT on partial SOI. The initial design latches at about 23V with forward voltage drop (VON) of 2V at 300A/cm2. The latest design shows increase of latch-up voltage close to 100V without significant expense of VON.


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Published: December 2012

We present a method for producing monolithically integrated CMOS optical filters with different and customerspecific responses. The filters are constituted by a Fabry-Perot resonator formed by two Bragg mirrors separated by a patterned cavity. The filter response can be tuned by changing the geometric parameters of the patterning, and consequently the cavity effective refractive index. In this way, many different filters can be produced at once on a single chip, allowing multichanneling. The filter has been designed, produced, and characterized. The results for a chip with 24 filters are presented.


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Published: October 2012

This paper presents a comparison between the superjunction LIGBT and the LDMOSFET in partial silicon-on-insulator (PSOI) technology in 0.18µm PSOIHV process. The superjunction drift region helps in achieving uniform electric field distribution in both structres but also contributes to the on-state current in the LIGBT.


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Published: October 2012

By this article an introduction of a highly robust metal track layout especially suitable for high current and temperature applications will be introduced. Starting with the reliability limitations normally observed for wide metal tracks, conclusions regarding the requirements for robust layout techniques will be drawn.


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Published: October 2012

Hermetic sealing is important regarding functionality and reliability for MEMS components. Typically this sealing is done on the wafer level using wafer bonding which simultaneously also provides mechanical protective caps. However, inner pressure and hermeticity testing and monitoring a still a critical issue; therefore, in this paper a test structure adapted to a MEMS foundry process for inertial sensors is introduced.


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Published: October 2012

State of the art polymer strippers were identified and successfully evaluated as interesting alternatives as CMOS-compatible wet activations for semiconductor wafer direct bonding processes, including both high and low temperature annealing for bond interface strengthening. The polymer strippers achieve both excellent surface cleaning and wafer bonding activation by hydrophilization and are therefore a very interesting alternative as semiconductor direct wafer bonding pre-treatment.


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