171 entries
Published: January 2013

The XT018 series is X-FAB’s 0.18 micron Modular High-voltage SOI CMOS Technology. Based on SOI wafers and the industrial standard single poly with up to six metal layers 0.18-micron drawn gate length process, integrated with high voltage and Non-Volatile-Memory modules, the platform is specifically designed for a new generation of cost-effective "Super Smart Power" technology; operating in temperature range of -40 to 175 °C.


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Published: April 2011

The XT06 Series completes X-FAB's 0.6 Micron Modular Mixed Signal Technology.
XT06 uses dielectric isolation on SOI wafers. This allows unrestricted 60 V high and low side operation of all devices. The process offers reduced parasitics which results in smaller crosstalk, reduced noise and better EMC characteristics. Thus XT06 allows innovative circuit design with reduced circuit complexity. CMOS as well as Bipolar Transistors are available with breakdown voltages up to 110V.
The 5 V CMOS core is compatible in design rules and transistor performance with state of the art 0.6μm CMOS processes.
For analog applications several capacitor and resistor devices are realized, using the double-poly architecture.


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Published: July 2013

XDH10 is X-Fab´s dielectric trench insulated smart power technology. Main target applications are analog switch ICs, driver ICs for capacitive, inductive and resistive loads and EL / piezo driver ICs for applications using 220V net supply. The typical breakdown voltage of the HV DMOS devices is >350V or >650V. The modular process combines DMOS, bipolar and CMOS processing steps that are compatible with dielectric insulation to provide a wide variety of MOS and bipolar devices with different voltage levels within a dielectric bi-directional high voltage trench insulation on the same die.


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Published: May 2012

XDM10 is X-Fab´s dielectric trench insulated smart power technology. Main target applications are analog switch ICs, driver ICs for capacitive, inductive and resistive loads and EL / piezo driver ICs for applications using 110V net supply. The typical breakdown voltage of the HV-DMOS devices is >350 V or >275V. The modular process combines DMOS, bipolar and CMOS processing steps that are compatible with dielectric insulation to provide a wide variety of MOS and bipolar devices with different voltage levels within a dielectric bi-directional high voltage trench insulation on the same die.


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Published: June 2013

Lifetime determination is one of the reliability key tasks to have an accurate estimation of the period of time that can still survive with a certain confidence level under the specific operating conditions to perform the respective function of the applications. Various reliability tests have been designed to reveal and assess the respective wear-out degradation mechanisms.


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Published: May 2013

This paper demonstrates a novel lateral superjunction (SJ) lateral insulated gate bipolar transistor (LIGBT) fabricated in 0.18μm partial silicon on insulator (PSOI) HV process. The results presented are based on extensive experimental measurements and numerical simulations.


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Published: April 2013

In this paper a modified MEMS foundry process allowing the production of 3D inertial sensors, such as accelerometers, gyroscopes and combinations, is introduced. The new MEMS process is suitable for a wide range of applications that use 3D accelerometers or gyroscopes. One-axis and three-axis designs can be produced with the same process, and the fabrication of complex inertial measurement units, in particular, the assembly process, is simplified.


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Published: May 2013

The filters are constituted by a Fabry-Perot resonator formed by two Bragg mirrors separated by a patterned cavity. The filter response can be tuned by changing the geometric parameters of the patterning, and consequently the cavity effective refractive index. In this way, many different filters can be produced at once on a single chip, allowing multichanneling. The filter has been designed, produced, and characterized. The results for a chip with 24 filters are presented.


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Published: May 2013

This paper presents versatile HV lateral JFET design method on 0.18μm SOI BCD technology to achieve variable Vth(pinch-off voltage) and Idsat, without DIBL effect over full operating Vds range and scalable breakdown voltage capability on both N-ch and P-ch JFET. The significant advantage of a HV JFET compared to depletion MOSFET is the lower area consumption in real circuit design which due to higher Idsat values at Vgs=0V.


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Published: December 2012

The fabrication of semiconductor devices, even in the area of customer oriented business, is one of the most complex production tasks in the world. A typical wafer production process consists of several hundred steps with numerous resources like equipments and operating staff. The optimal assignment of each resource at each time for a certain number of wafers is vital for a efficient production process. Several demands defined by the customers and facility management must be taken into consideration with the objective to find the best tradeoff between the different needs.


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