104 entries, filtered by: Paper
Published: July 2011

An enhancement-mode Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) device has been developed in 0.13μm technology platform. The single-transistor (1-T) SONOS device in NOR Flash memory array utilizes n-channel cells. The development of 1-T SONOS is not an easy feat due to many disturbs experienced by the cells during operation.


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Published: July 2011

In low leakage MOS device fabrication, careful pn junction design is critical to control overall device leakage, such as Band-To-Band Tunneling (BTBT) and Gate-Induced Drain Leakage (GIDL) that are always taken into consideration by device designers. Source/Drain implantation also play a very important role in suppressing silicon dislocation effect, which increases implanted species transient-enhanced diffusion (TED) and induces shallow-junction leakage.


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Published: June 2011

Photo detector integrated circuits (PDIC) require high-sensitivity and high-bandwidth photo diodes for the latest generation of Blu-ray data storage devices. Due to the very short 405nm wavelength used, carriers are generated close to the surface. Standard photo diodes have only a low sensitivity for blue light. Therefore, special adapted photo diodes are necessary to support sensitivity higher than 0.25A/W for a 405nm wavelength.


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Published: June 2011

In this paper, micromachined acceleration sensors as ready-to-use Intellectual-Property-Blocks (IP-Blocks) are introduced. These standard elements are available for a special surface micromachining foundry technology. They are ready to use, characterized and qualified design elements, which can be customized by changing the peripheral elements such as bond pads, and allow the fast prototyping and production start of high-performance inertial sensors.


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Published: May 2011

In this paper we present a modular trench isolated high voltage SOI process with the possibility to integrate various types of high voltage transistors. The integration of these additional 650 V devices takes place in a modular approach which allows a high process flexibility to support different applications with a minimum number of additional or changed process steps.


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Published: May 2011

Successful integration of 100V LDMOS devices in 0.35μm CMOS technology is presented in this paper. These integrated devices are enhanced N-type and P-type LDMOS which are compatible with thin (14nm) and thick (40nm) layers of gate oxide. A breakdown voltage of more than 100V with RDS (ON) =200/180mΩ.mm2 for N-type LDMOS and RDS (ON) =690/640mΩ.mm2 for P-type LDMOS with 14nm/40nm gate oxide thickness.


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Published: May 2011

This paper demonstrates and explains the effects of hot carrier injection and interface charge trapping correlated with impact ionization under normal on-state conditions in a highly dense low-resistance Super-Junction LDMOSFET. The study is done through extensive experimental measurements and numerical simulations using advanced trap models.


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Published: April 2011

Silicon photodiode integrated with CMOS has been in extensive study for the past ten years due to its wide use in applications such as short-distance communication, VCD players, ambient light sensors and many other intelligent systems. In recent years, high speed blue-ray DVD is replacing conventional DVD due to its larger storage capacity and higher speed. In this work, the photodiode optimized for blue ray is fully integrated with standard 0.35um CMOS process and the bandwidth dependency upon thermal process and epitaxial material is investigated.


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Published: March 2011

Drastically device dimension shrinkage and rigorous requirement in automotive era puts Negative Bias Temperature Instability (NBTI) at the forefront of reliability issue recently. The PMOS parametric degradation during negative bias high temperature aging can depend on many process variables of the manufacturing flow. A study was carried out to explore the process related dependencies for high voltage PMOS transistor and to increase the device robustness against NBTI stress. In this papers, the process impact on the NBTI degradation were discussed. This investigation work provides methods for significant suppression of the NBTI degradation with silicon rich oxide (SRO) inter layer dielectric (ILD) liner and two-step gate oxidation.


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Published: March 2011

A study has been carried out to improve metal-insulator-metal (MIM) capacitor's capacitance density and linearity performance. The scopes of the study included single MiM and stack MIM structures. Different dielectric schemes were evaluated with their corresponding capacitance density, breakdown voltages and linearity coefficient to voltage and temperature variation etc. characterised.


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