104 entries, filtered by: Paper
Published: October 2012

Hermetic sealing is important regarding functionality and reliability for MEMS components. Typically this sealing is done on the wafer level using wafer bonding which simultaneously also provides mechanical protective caps. However, inner pressure and hermeticity testing and monitoring a still a critical issue; therefore, in this paper a test structure adapted to a MEMS foundry process for inertial sensors is introduced.


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Published: October 2012

State of the art polymer strippers were identified and successfully evaluated as interesting alternatives as CMOS-compatible wet activations for semiconductor wafer direct bonding processes, including both high and low temperature annealing for bond interface strengthening. The polymer strippers achieve both excellent surface cleaning and wafer bonding activation by hydrophilization and are therefore a very interesting alternative as semiconductor direct wafer bonding pre-treatment.


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Published: October 2012

In this paper, optimization and physical scaling of the SONOS ONO triple layer are extensively evaluated, with detailed characterization of the Flash cell behavior. Reliability tests have demonstrated high temperature endurance and long-term data retention. The results have shown that the reliability requirement is attainable even with down scaling of the vertical component of the oxynitride charge trapping layer, which makes it feasible to operate the cell at a lower programming voltage.


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Published: October 2012

This Inter-poly Oxide-Nitride-Oxide (ONO) dielectric film has been widely used as dielectric films in stacked gate Flash memory devices. The ONO dielectric film plays an important role in ensuring good reliability in flash memory devices. In this paper, the characteristics of ONO dielectric films have been analyzed.


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Published: September 2012

Reliability tests assessment are used to evaluate the quality of different process schemes of MIM capacitors. Typically, VRAMP tests can be used to check for extrinsics; which are common and popular method used for evaluating yield issues and early life failures (in which the product failures in ppm level); while TDDB tests are used to determine the intrinsic quality of the capacitor dielectrics; thus the lifetime will be extrapolated accordingly from its dependency from accelerated tests at different higher stress conditions down to the corresponding use condition.


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Published: June 2012

This paper demonstrates and discusses novel “three dimensional” silicon based junction isolation/termination solutions suitable for high density ultra-low-resistance Lateral Super-Junction structures.


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Published: April 2012

Inline defect control systems are used across the semiconductor industry for detection of process failures like equipment issues or yield problems. Besides to the goal to improve the yield of each process, it may have a negative influence on factory performance as well. The measurement of all lots in all defect control monitors of a process is not feasible, even when there are bottleneck situations.


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Published: April 2012

In a typical ASIC semiconductor facility, there are hundreds of products processed on dozens of different equipments with unequal characteristics. Sequence depended equipment setups, failures, preventive maintenance and product specific re-entrant flows cause a high variability in factory performance measures. Also different customer demands, which are natural in the foundry business, should be taken into account (e.g. delivery dates or throughput). To reduce the variability and to improve the factory performance a robust and efficient dispatching and scheduling strategy is vital.


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Published: April 2012

The article at hand presents the results of thermoelectrical simulations of migration effects in integrated interconnect systems in comparison to measurement data. The simulation concept will be described and the output values as mass flux divergence and time-to-failure (TTF) will be discussed.


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Published: April 2012

The huge demand for high voltage, high current power devices on Silicon on Chip (SoC) has led to the development of Lateral IGBT (LIGBT), touted as the best candidate to serve these two purposes. This paper is the first to review the research works on LIGBTs published till now. The LIGBTs are categorized into four types based on different technologies applied, mainly Junction Isolation (JI), Silicon On Insulator (SOI), Partial SOI (PSOI) and Membrane, and ten varieties based on their device mechanisms, such as Reverse Conducting, Trench Gate and Super Junction.


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