14 entries, filtered by: Simulation
Published: April 2012

The article at hand presents the results of thermoelectrical simulations of migration effects in integrated interconnect systems in comparison to measurement data. The simulation concept will be described and the output values as mass flux divergence and time-to-failure (TTF) will be discussed.


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Published: June 2009

A combination of conventional cross sectional process and device simulations combined with top down and 3D device simulations have been used to design and optimise the integration of a 100V Lateral DMOS (LDMOS) device for high side bridge applications. This combined simulation approach can streamline the device design process and gain important information about end effects which are lost from 2D cross sectional simulations. Design solutions to negate detrimental end effects are proposed and optimised by top down and 3D simulations and subsequently proven on tested silicon.


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Published: July 2008

In this paper, a 40V versatile HV LDMOS technology with lower Rdson has been developed in the existing 0.18μm LV CMOS process. The HV LDMOS are designed by using DOE concept on the simulation results from T-supreme followed by Medici.


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Published: July 2008

Designing of high voltage LDMOS with a reduced surface field (RESURF) structure have been investigated to achieve the optimum figure of merit, maximum breakdown voltage accompanied with low on resistance. The drift region profile and device geometry plays important role to achieve target breakdown voltage of 80V. The electrical behaviors of the designed high voltage LDMOS for both on state and off state conditions are discussed analytically in this paper.


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Published: July 2008

Rapid increasing demand towards high voltage MOSFETs device integrated in low voltage CMOS analog and digital circuits for automobile and power management application has driven the development of 0.18um high voltage lateral diffused MOSFET (LDMOS) which capable to have 80V breakdown voltage. During designing this high voltage LDMOS, it is observed that the device performance is very dependent towards the device geometry particularly poly overlap length on STI. Thus, in this paper, the effects of poly overlap length on STI plate for high voltage LDNMOS have been studied extensively during the off-state condition.


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Published: July 2008

In this work an attempt is made to extract Dual Pearson moments from 1-D Monte Carlo simulated profiles, and these moments are used for 2-D simulations. This approach gives same accurate implant profile as Monte Carlo, but simulation time is significantly reduced.


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Published: July 2008

With the further scaling down of CMOS devices, hot carrier induced degradation has become one of the most important reliability concerns. In the hot carrier effect, carriers are accelerated by the channel electric fields and become trapped in the oxide. These trapped charges cause time dependent shifts in measured device parameters.


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Published: May 2008

The long term isolation properties of deep trenches in thick SOI have been investigated by current-voltage characteristics. A strong change of the measured trench leakage current was observed depending on the applied voltage. Further on a marked decrease of the leakage current was observed depending on the duration and polarity of the applied stress.


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Published: December 2007

To fulfill the current market demand of smart power IC’s an attempt was made to incorporate the high voltage devices in the current baseline of 0.18 micron low voltage process. Circular high voltage structure proposes for some advantages such as higher breakdown voltage, lower leakage current, less area and etc over the normal structure. The NMOS & PMOS both types of transistors are optimized in terms of their structure and process condition to achieve large breakdown voltage with lower Ron value.


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Published: April 2006

A wafer-level testing method is investigated for an early stage of the manufacturing process applied to accelerometers. The approach consists of performing optical measurement of the modal responses of the MEMS structures, and uses this information in an inverse identification algorithm based on a FE model.


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