14 entries, filtered by: Simulation
Published: September 2005

During the evolution of RF bipolar transistors, much efforts were spent to optimize the base design. Device engineers came up with concepts like graded dopant profiles, SiGe and SiGe:C base layers, elevated base structures, etc. Regarding the collector, selectively implanted collectors (SIC) were introduced to increase both the cutoff frequency ft and the maximum frequency of oscillation fmax. In this work we focus on the collector-emitter breakdown voltage BVCE0 and its relation to ft for differently designed SICs of Si-based RF bipolar transistors.


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Published: April 2006

A wafer-level testing method is investigated for an early stage of the manufacturing process applied to accelerometers. The approach consists of performing optical measurement of the modal responses of the MEMS structures, and uses this information in an inverse identification algorithm based on a FE model.


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Published: December 2007

To fulfill the current market demand of smart power IC’s an attempt was made to incorporate the high voltage devices in the current baseline of 0.18 micron low voltage process. Circular high voltage structure proposes for some advantages such as higher breakdown voltage, lower leakage current, less area and etc over the normal structure. The NMOS & PMOS both types of transistors are optimized in terms of their structure and process condition to achieve large breakdown voltage with lower Ron value.


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Published: May 2008

The long term isolation properties of deep trenches in thick SOI have been investigated by current-voltage characteristics. A strong change of the measured trench leakage current was observed depending on the applied voltage. Further on a marked decrease of the leakage current was observed depending on the duration and polarity of the applied stress.


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Published: July 2008

In this paper, a 40V versatile HV LDMOS technology with lower Rdson has been developed in the existing 0.18μm LV CMOS process. The HV LDMOS are designed by using DOE concept on the simulation results from T-supreme followed by Medici.


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Published: July 2008

Designing of high voltage LDMOS with a reduced surface field (RESURF) structure have been investigated to achieve the optimum figure of merit, maximum breakdown voltage accompanied with low on resistance. The drift region profile and device geometry plays important role to achieve target breakdown voltage of 80V. The electrical behaviors of the designed high voltage LDMOS for both on state and off state conditions are discussed analytically in this paper.


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Published: July 2008

Rapid increasing demand towards high voltage MOSFETs device integrated in low voltage CMOS analog and digital circuits for automobile and power management application has driven the development of 0.18um high voltage lateral diffused MOSFET (LDMOS) which capable to have 80V breakdown voltage. During designing this high voltage LDMOS, it is observed that the device performance is very dependent towards the device geometry particularly poly overlap length on STI. Thus, in this paper, the effects of poly overlap length on STI plate for high voltage LDNMOS have been studied extensively during the off-state condition.


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Published: July 2008

In this work an attempt is made to extract Dual Pearson moments from 1-D Monte Carlo simulated profiles, and these moments are used for 2-D simulations. This approach gives same accurate implant profile as Monte Carlo, but simulation time is significantly reduced.


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Published: July 2008

With the further scaling down of CMOS devices, hot carrier induced degradation has become one of the most important reliability concerns. In the hot carrier effect, carriers are accelerated by the channel electric fields and become trapped in the oxide. These trapped charges cause time dependent shifts in measured device parameters.


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Published: November 2008

The work presented here shows a change in migration behaviour of a transferred AlCu metallization system. Different failure mechanisms in metallization are known. Migration effects like electro-, thermo- and stress migration are the main failure mechanisms in a metallization. This study shows the detection and exploration of a significant change in the migration mechanism of a wide lines of a top level interconnect of a standard metallization. The study demonstrates the differences of the transferred metallization system and the influence for the degradation behaviour and reliability.


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