22 entries, filtered by: SOI
Published: January 2013

The XT018 series is X-FAB’s 0.18 micron Modular High-voltage SOI CMOS Technology. Based on SOI wafers and the industrial standard single poly with up to six metal layers 0.18-micron drawn gate length process, integrated with high voltage and Non-Volatile-Memory modules, the platform is specifically designed for a new generation of cost-effective "Super Smart Power" technology; operating in temperature range of -40 to 175 °C.


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Published: April 2011

The XT06 Series completes X-FAB's 0.6 Micron Modular Mixed Signal Technology.
XT06 uses dielectric isolation on SOI wafers. This allows unrestricted 60 V high and low side operation of all devices. The process offers reduced parasitics which results in smaller crosstalk, reduced noise and better EMC characteristics. Thus XT06 allows innovative circuit design with reduced circuit complexity. CMOS as well as Bipolar Transistors are available with breakdown voltages up to 110V.
The 5 V CMOS core is compatible in design rules and transistor performance with state of the art 0.6μm CMOS processes.
For analog applications several capacitor and resistor devices are realized, using the double-poly architecture.


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Published: July 2013

XDH10 is X-Fab´s dielectric trench insulated smart power technology. Main target applications are analog switch ICs, driver ICs for capacitive, inductive and resistive loads and EL / piezo driver ICs for applications using 220V net supply. The typical breakdown voltage of the HV DMOS devices is >350V or >650V. The modular process combines DMOS, bipolar and CMOS processing steps that are compatible with dielectric insulation to provide a wide variety of MOS and bipolar devices with different voltage levels within a dielectric bi-directional high voltage trench insulation on the same die.


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Published: May 2012

XDM10 is X-Fab´s dielectric trench insulated smart power technology. Main target applications are analog switch ICs, driver ICs for capacitive, inductive and resistive loads and EL / piezo driver ICs for applications using 110V net supply. The typical breakdown voltage of the HV-DMOS devices is >350 V or >275V. The modular process combines DMOS, bipolar and CMOS processing steps that are compatible with dielectric insulation to provide a wide variety of MOS and bipolar devices with different voltage levels within a dielectric bi-directional high voltage trench insulation on the same die.


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Published: May 2013

This paper demonstrates a novel lateral superjunction (SJ) lateral insulated gate bipolar transistor (LIGBT) fabricated in 0.18μm partial silicon on insulator (PSOI) HV process. The results presented are based on extensive experimental measurements and numerical simulations.


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Published: May 2013

This paper presents versatile HV lateral JFET design method on 0.18μm SOI BCD technology to achieve variable Vth(pinch-off voltage) and Idsat, without DIBL effect over full operating Vds range and scalable breakdown voltage capability on both N-ch and P-ch JFET. The significant advantage of a HV JFET compared to depletion MOSFET is the lower area consumption in real circuit design which due to higher Idsat values at Vgs=0V.


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Published: December 2012

This paper evaluates the technique used to improve the latching characteristics of the 200V n-type superjunction (SJ) LIGBT on partial SOI. The initial design latches at about 23V with forward voltage drop (VON) of 2V at 300A/cm2. The latest design shows increase of latch-up voltage close to 100V without significant expense of VON.


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Published: October 2012

This paper presents a comparison between the superjunction LIGBT and the LDMOSFET in partial silicon-on-insulator (PSOI) technology in 0.18µm PSOIHV process. The superjunction drift region helps in achieving uniform electric field distribution in both structres but also contributes to the on-state current in the LIGBT.


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Published: June 2012

This paper demonstrates and discusses novel “three dimensional” silicon based junction isolation/termination solutions suitable for high density ultra-low-resistance Lateral Super-Junction structures.


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Published: June 2011

In this paper, micromachined acceleration sensors as ready-to-use Intellectual-Property-Blocks (IP-Blocks) are introduced. These standard elements are available for a special surface micromachining foundry technology. They are ready to use, characterized and qualified design elements, which can be customized by changing the peripheral elements such as bond pads, and allow the fast prototyping and production start of high-performance inertial sensors.


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