104 entries, filtered by: Paper
Published: September 2011

A study on the effect of process fabrication for MIM capacitors analog matching performance was carried out, impacts from the MIM dielectrics, capacitor top and bottom metal materials, capacitor metal etch, wet cleaning, annealing process will be revealed by comparing the Pelgrom coefficients, i.e. the dependence of difference in capacitance of the matching pairs with respect to their corresponding square root of capacitor areas, the smaller the difference the better the matching.


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Published: September 2011

Diodes inherent in a CMOS process are light sensitive and could be exploited as photodetectors. To detect light the photo generated carriers need to be separated by the electrical field of an internal pn junction. They are either generated inside the depletion region or can get there by diffusion. The depth where these carriers are generated depends strongly on the wavelength. The generation profile, the pn junction depth and the diffusion length all impact the spectral sensitivity.


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Published: September 2011

This paper presents a simple but effective way to improve an NMOS transistor’s ESD robustness for use in I/O pads. Simulation and physical failure analysis has been performed to identify the source of the ESD failure. Process splits have been performed primarily at LDD (Lightly Doped Drain) implant and salicidation process based on data presented in this paper.


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Published: September 2011

Using a trench isolated 650V quasi-vertical n-channel DMOS as a starting point several new 650V transistor types have been evaluated. Mainly by design measures a 650V depletion DMOS, a 650V PMOS and a 650V IGBT were created for a modular integration into the process flow.


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Published: July 2011

In low leakage MOS device fabrication, careful pn junction design is critical to control overall device leakage, such as Band-To-Band Tunneling (BTBT) and Gate-Induced Drain Leakage (GIDL) that are always taken into consideration by device designers. Source/Drain implantation also play a very important role in suppressing silicon dislocation effect, which increases implanted species transient-enhanced diffusion (TED) and induces shallow-junction leakage.


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Published: July 2011

An enhancement-mode Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) device has been developed in 0.13μm technology platform. The single-transistor (1-T) SONOS device in NOR Flash memory array utilizes n-channel cells. The development of 1-T SONOS is not an easy feat due to many disturbs experienced by the cells during operation.


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Published: June 2011

In this paper, micromachined acceleration sensors as ready-to-use Intellectual-Property-Blocks (IP-Blocks) are introduced. These standard elements are available for a special surface micromachining foundry technology. They are ready to use, characterized and qualified design elements, which can be customized by changing the peripheral elements such as bond pads, and allow the fast prototyping and production start of high-performance inertial sensors.


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Published: June 2011

Photo detector integrated circuits (PDIC) require high-sensitivity and high-bandwidth photo diodes for the latest generation of Blu-ray data storage devices. Due to the very short 405nm wavelength used, carriers are generated close to the surface. Standard photo diodes have only a low sensitivity for blue light. Therefore, special adapted photo diodes are necessary to support sensitivity higher than 0.25A/W for a 405nm wavelength.


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Published: May 2011

This paper demonstrates and explains the effects of hot carrier injection and interface charge trapping correlated with impact ionization under normal on-state conditions in a highly dense low-resistance Super-Junction LDMOSFET. The study is done through extensive experimental measurements and numerical simulations using advanced trap models.


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Published: May 2011

Successful integration of 100V LDMOS devices in 0.35μm CMOS technology is presented in this paper. These integrated devices are enhanced N-type and P-type LDMOS which are compatible with thin (14nm) and thick (40nm) layers of gate oxide. A breakdown voltage of more than 100V with RDS (ON) =200/180mΩ.mm2 for N-type LDMOS and RDS (ON) =690/640mΩ.mm2 for P-type LDMOS with 14nm/40nm gate oxide thickness.


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