104 entries, filtered by: Paper
Published: October 2012

State of the art polymer strippers were identified and successfully evaluated as interesting alternatives as CMOS-compatible wet activations for semiconductor wafer direct bonding processes, including both high and low temperature annealing for bond interface strengthening. The polymer strippers achieve both excellent surface cleaning and wafer bonding activation by hydrophilization and are therefore a very interesting alternative as semiconductor direct wafer bonding pre-treatment.


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Published: October 2012

Hermetic sealing is important regarding functionality and reliability for MEMS components. Typically this sealing is done on the wafer level using wafer bonding which simultaneously also provides mechanical protective caps. However, inner pressure and hermeticity testing and monitoring a still a critical issue; therefore, in this paper a test structure adapted to a MEMS foundry process for inertial sensors is introduced.


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Published: October 2012

By this article an introduction of a highly robust metal track layout especially suitable for high current and temperature applications will be introduced. Starting with the reliability limitations normally observed for wide metal tracks, conclusions regarding the requirements for robust layout techniques will be drawn.


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Published: October 2012

This paper presents a comparison between the superjunction LIGBT and the LDMOSFET in partial silicon-on-insulator (PSOI) technology in 0.18µm PSOIHV process. The superjunction drift region helps in achieving uniform electric field distribution in both structres but also contributes to the on-state current in the LIGBT.


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Published: September 2012

Gate oxide early breakdown was investigated. It was verified that the gate oxide quality is good and failure was due to extrinsic causes. The failure, which was localized at the edge of LOCOS was similar to Kooi effect. However, investigations showed that it was due to nitridation occured during high temperature nitrogen anneal. Investigation methods to find the root cause of failure were explained. Alternative methods to solve the failure were explored; including thickening the sacrificial oxide layer and changing the nitrogen anneal process sequence. Final solution was chosen based on PCM stress test, QBD and TDDB result with minimal process change.


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Published: September 2012

Reliability tests assessment are used to evaluate the quality of different process schemes of MIM capacitors. Typically, VRAMP tests can be used to check for extrinsics; which are common and popular method used for evaluating yield issues and early life failures (in which the product failures in ppm level); while TDDB tests are used to determine the intrinsic quality of the capacitor dielectrics; thus the lifetime will be extrapolated accordingly from its dependency from accelerated tests at different higher stress conditions down to the corresponding use condition.


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Published: June 2012

This paper demonstrates and discusses novel “three dimensional” silicon based junction isolation/termination solutions suitable for high density ultra-low-resistance Lateral Super-Junction structures.


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Published: April 2012

The huge demand for high voltage, high current power devices on Silicon on Chip (SoC) has led to the development of Lateral IGBT (LIGBT), touted as the best candidate to serve these two purposes. This paper is the first to review the research works on LIGBTs published till now. The LIGBTs are categorized into four types based on different technologies applied, mainly Junction Isolation (JI), Silicon On Insulator (SOI), Partial SOI (PSOI) and Membrane, and ten varieties based on their device mechanisms, such as Reverse Conducting, Trench Gate and Super Junction.


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Published: April 2012

The article at hand presents the results of thermoelectrical simulations of migration effects in integrated interconnect systems in comparison to measurement data. The simulation concept will be described and the output values as mass flux divergence and time-to-failure (TTF) will be discussed.


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Published: April 2012

In a typical ASIC semiconductor facility, there are hundreds of products processed on dozens of different equipments with unequal characteristics. Sequence depended equipment setups, failures, preventive maintenance and product specific re-entrant flows cause a high variability in factory performance measures. Also different customer demands, which are natural in the foundry business, should be taken into account (e.g. delivery dates or throughput). To reduce the variability and to improve the factory performance a robust and efficient dispatching and scheduling strategy is vital.


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