114 entries, filtered by: Paper
Published: May 2015

Ultraviolet (UV) sensitive Silicon based photodiodes integrated into a high-voltage modular 0.35 μm CMOS technology are presented. 


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Published: May 2015

This paper presents a new SOI BCD technology at the 0.18μm node to fulfill the requirements for smart power IC technology targeted for automotive application. Built on a 1.8V and 5.0V CMOS core, there are 40V and 60V rated N/Pch MOS, with 25mΩ.mm2 RonA/57V BVdss having been achieved for the 40V NMOS with excellent process stability.


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Published: March 2015

The design of a system containing integrated MEMS is still a task which requires deep knowledge of the MEMS process itself. Even with the availability of COT MEMS foundry processes, which support the design of MEMS according to process-specific design rules, the quality of results heavily depends on the skills and know-how of the involved designers. Reasons for this are the lack of a sufficient design automation, which would implement and verify parts of the expert knowledge, as well as the missing process abstraction, which would encapsulate the foundry-specific rules and parameters.


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Published: March 2015

For gate driver ICs in three phase power applications level shifters with more than 900V operating voltage are required. The extension of the voltage rating of an existing trench isolated SOI process was done with different device concepts: Serial stacking of lower voltage devices was evaluated as an alternative approach to conventional quasi-vertical and charge compensated lateral devices which need layout and material modifications. 


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Published: September 2014

For a high robust metallization it is necessary to solve different problems related to migration mechanisms and thermo-mechanical stress in the material. Extended operating conditions and challenging assembling processes influence stress behaviour in chip corners. Typically the corner area of the chip is excluded for use. For higher stress load the forbidden area increases. But effort for demanding mission profiles of a product should not cumulative in increasing chip size. Simulation can help to a better understanding of mechanical stress in the chip corner and chip-package interaction.


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Published: September 2014

The miniaturization process of CMOS components creates new challenges for the development of integrated circuits. Especially the connections with a tungsten via between two metal layers can be a problem. Changes in geometry can bear on reliability problems. For a robust metallization design it is necessary to know, how strong the influence of the tungsten via alignment affects the physical behavior. 


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Published: August 2014

Serial stacking of high voltage devices in a SOI process to achieve higher operating voltages is an alternative approach to layout and material modifications being necessary in a conventional quasi-vertical approach. Based on a sufficient 900 V trench isolation the stacking was first tested with existing lower voltage diodes and compared to new 900 V diodes with the conventional quasi-vertical construction.


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Published: June 2014

For industrial and automotive applications a 0.35μm aluminium CMOS process is one of the common used technologies. An increasing demand on extended operating conditions must be fulfilled especially for high current carrying metal lines. A new design concept is to modify the shape of these lines. The use of slots especially of octahedron slots demonstrates a better robustness towards electromigration in upper metallization layers. Another benefit is the good reliability under pulsed DC conditions primarily in comparison to wide homogeneous filled metal lines.


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Published: July 2013

For most devices sitting on SOI wafer, there is a consideration of backside coupling effect. This phenomenon becomes catastrophic if the device sits on the SOI wafer is an IGBT which consists n-p-n-p structure and employs both the partial SOI and DTI technique. Earlier leakage had been found during development of 200V superjunction lateral IGBT (SJ LIGBT) on partial SOI.


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Published: June 2013

Lifetime determination is one of the reliability key tasks to have an accurate estimation of the period of time that can still survive with a certain confidence level under the specific operating conditions to perform the respective function of the applications. Various reliability tests have been designed to reveal and assess the respective wear-out degradation mechanisms.


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