40 entries, filtered by: High-Voltage
Published: November 2011

The power semiconductor industry has grown steadily in past two decades from $2.7 billion in 1992 and is expected to reach $13.1 billion in annual sales volume this year due to rapid proliferation of power electronics in many fields like telecommunication, automotive, new renewable energy system and energy conversion application. Among power transistor products, sales of modules built with Insulated Gate Bipolar Transistor (IGBT) are expected to increase 10 percent to $2.5 billion this year.
This paper gives an overview to different types of IGBTs available in current market as well as those under development.


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Published: September 2011

Using a trench isolated 650V quasi-vertical n-channel DMOS as a starting point several new 650V transistor types have been evaluated. Mainly by design measures a 650V depletion DMOS, a 650V PMOS and a 650V IGBT were created for a modular integration into the process flow.


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Published: May 2011

This paper demonstrates and explains the effects of hot carrier injection and interface charge trapping correlated with impact ionization under normal on-state conditions in a highly dense low-resistance Super-Junction LDMOSFET. The study is done through extensive experimental measurements and numerical simulations using advanced trap models.


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Published: May 2011

Successful integration of 100V LDMOS devices in 0.35μm CMOS technology is presented in this paper. These integrated devices are enhanced N-type and P-type LDMOS which are compatible with thin (14nm) and thick (40nm) layers of gate oxide. A breakdown voltage of more than 100V with RDS (ON) =200/180mΩ.mm2 for N-type LDMOS and RDS (ON) =690/640mΩ.mm2 for P-type LDMOS with 14nm/40nm gate oxide thickness.


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Published: May 2011

In this paper we present a modular trench isolated high voltage SOI process with the possibility to integrate various types of high voltage transistors. The integration of these additional 650 V devices takes place in a modular approach which allows a high process flexibility to support different applications with a minimum number of additional or changed process steps.


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Published: March 2011

Drastically device dimension shrinkage and rigorous requirement in automotive era puts Negative Bias Temperature Instability (NBTI) at the forefront of reliability issue recently. The PMOS parametric degradation during negative bias high temperature aging can depend on many process variables of the manufacturing flow. A study was carried out to explore the process related dependencies for high voltage PMOS transistor and to increase the device robustness against NBTI stress. In this papers, the process impact on the NBTI degradation were discussed. This investigation work provides methods for significant suppression of the NBTI degradation with silicon rich oxide (SRO) inter layer dielectric (ILD) liner and two-step gate oxidation.


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Published: August 2010

The XHB06 is X-FAB's 0.6 Micron High-Voltage Bipolar CMOS DMOS (BCD) Technology, optimized for applications requiring operating voltages of 5V to 30V. Main target applications are power management, RF circuits and high precision analog applications mixed with digital parts for Telecommunication, Consumer, Automotive and Industrial products. The digital part is fully compatible with X-CMOS 0.6 process family.


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Published: July 2010

Emerging applications in the field of lithium-ion battery management and Power over Ethernet require operating voltages of up to 100V, robust primitive devices and low on-resistance. X-FAB’s enhanced 0.35 micrometer high-voltage foundry process XH035 offers these features combined with high reliability and a small silicon footprint.


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Published: July 2010

A novel 0.18μm 200V integrated technology based on Partial SOI and lateral Super Junctions devices is presented. The dielectric isolation inherent in SOI allows simple and areaefficient integration of electrically floating CMOS and HV devices while removing all substrate carrier injection-related parasitic effects. The Super Junctions give a competitively low on-resistance of HVMOS and provide a wide-range breakdown voltage-scaling capability.


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Published: June 2009

A combination of conventional cross sectional process and device simulations combined with top down and 3D device simulations have been used to design and optimise the integration of a 100V Lateral DMOS (LDMOS) device for high side bridge applications. This combined simulation approach can streamline the device design process and gain important information about end effects which are lost from 2D cross sectional simulations. Design solutions to negate detrimental end effects are proposed and optimised by top down and 3D simulations and subsequently proven on tested silicon.


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