37 entries, filtered by: Reliability
Published: October 2009

At high temperature, designers are faced with additional technological and design challenges. These issues and how to address them are discussed in this presentation. The webinar looks at X-FAB's high temperature solutions, in particular its latest High Temperature Modular CMOS process (XA035), a comprehensive CMOS offering with High Voltage (HV), RF, and EEPROM integration that is suitable for temperatures up to 175C. The presentation also covers high temperature modelling, application specific reliability and design for reliability.


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Published: July 2009

This paper presents an investigation of low oxide breakdown voltage on polysilicon-oxide-diffusion (POD) capacitor. The dielectric was 7 nm thermal oxide which was grown simultaneously for MOS transistor as gate oxide. The V-Ramp measurement showed bimodal distribution of Vbd with one circular patch having < 7 V instead of the target Vbd (10 V). The size of the patch depends on the POD capacitor area. This behavior was not observed on gate oxide of MOS transistor and 22.5 nm POD capacitor. Process partition check, including wafer orientation and wafer slot arrangement was conducted. The specific process step causing the patch signature has been identified successfully.


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Published: November 2008

The work presented here shows a series of engineering runs to improve the AC HCI lifetime for a 0.60μm NMOS. The conventional method of increasing NLDD energy and reducing NLDD dose did not achieve significant improvement. The study concludes that tilting the NLDD implant, coupled with prolonging the NLDD anneal and increasing the Poly CD can improve the lifetime significantly. A short HCI test was performed to compare the response of different splits.


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Published: November 2008

The work presented here show the impact of different reticle transmission ratio (macro pattern density) to metal profile and CD bias of metal etch process. These impacts are due to macro loading and passivation effects differ when pattern density at wafer level changed. We also try to investigate the impact of passivation gas to above phenomenon.


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Published: November 2008

The work presented here shows a change in migration behaviour of a transferred AlCu metallization system. Different failure mechanisms in metallization are known. Migration effects like electro-, thermo- and stress migration are the main failure mechanisms in a metallization. This study shows the detection and exploration of a significant change in the migration mechanism of a wide lines of a top level interconnect of a standard metallization. The study demonstrates the differences of the transferred metallization system and the influence for the degradation behaviour and reliability.


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Published: November 2008

Wafer Level Reliability Gate Oxide Integrity tests such as voltage-ramped and constant current stress have been conducted on area plate-type, poly edge and STI edge intensive test structures. The WLR tests are required for qualifying the process of integrating 3.3 nm and 12.5 nm dual gate oxide operated under the bias of 1.8V and 5V respectively on a single chip.


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Published: November 2008

Several methods have been investigated for gettering impurities during CMOS processing, in order to achieve high-quality oxides on thick SOI. The use of buried implants, buried polysilicon, surface implants, and isolation trenches was found to significantly improve the oxide quality in each case


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Published: July 2008

With the further scaling down of CMOS devices, hot carrier induced degradation has become one of the most important reliability concerns. In the hot carrier effect, carriers are accelerated by the channel electric fields and become trapped in the oxide. These trapped charges cause time dependent shifts in measured device parameters.


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Published: July 2008

Hot carriers, the high kinetic energy carriers due to high electric field in the channel region, are injected into the gate oxide and form interface states, which in turns causes degradation of MOS device performance. The hot carrier effect has become more severe as the device size continues to scale down to submicron range. This aging phenomenon that threatens the circuit and product lifetimes warrants it to be considered as the key challenge in reliability.


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Published: July 2008

Experimental condition of thin SAB Oxide around 350Å coupling with 400Å Contact SiON film has exhibited the worst data retention behavior in One Time Programmable (OTP) & Multiple Time Programmable (MTP) memory device.


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