104 entries, filtered by: Paper
Published: June 2009

A combination of conventional cross sectional process and device simulations combined with top down and 3D device simulations have been used to design and optimise the integration of a 100V Lateral DMOS (LDMOS) device for high side bridge applications. This combined simulation approach can streamline the device design process and gain important information about end effects which are lost from 2D cross sectional simulations. Design solutions to negate detrimental end effects are proposed and optimised by top down and 3D simulations and subsequently proven on tested silicon.


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Published: November 2008

The work presented here shows a series of engineering runs to improve the AC HCI lifetime for a 0.60μm NMOS. The conventional method of increasing NLDD energy and reducing NLDD dose did not achieve significant improvement. The study concludes that tilting the NLDD implant, coupled with prolonging the NLDD anneal and increasing the Poly CD can improve the lifetime significantly. A short HCI test was performed to compare the response of different splits.


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Published: November 2008

Traditional cross-sectional sample treatment methods such as BOE (Buffered oxide etch), can easily highlight Titanium Salicide (TiSi2) by etching away the TiSi2 (thus creating voids or cavitations) with no impact on the silicon underneath the salicide. However, this method does not work for devices using Cobalt Salicide (CoSi2) technology. The work presented here is to introduce a special etchant or chemical mix that will etch the Cobalt Salicide (CoSi2), with no significant impact on the silicon underneath the salicide layer.


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Published: November 2008

The fast scanning mechanism of High Current batch Implanter is achieved by spinning the wafer disk with angular speed more than 1200 Rotation-Per-Minute (RPM). If particles hit device wafers during implant it can cause serious damage to device structure. Particle generation areas are mainly from Source terminal, Accelerator Column, Plasma Flood Gun (PFG) and beam line wall.


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Published: November 2008

The work presented here show the impact of different reticle transmission ratio (macro pattern density) to metal profile and CD bias of metal etch process. These impacts are due to macro loading and passivation effects differ when pattern density at wafer level changed. We also try to investigate the impact of passivation gas to above phenomenon.


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Published: November 2008

The work presented here shows a change in migration behaviour of a transferred AlCu metallization system. Different failure mechanisms in metallization are known. Migration effects like electro-, thermo- and stress migration are the main failure mechanisms in a metallization. This study shows the detection and exploration of a significant change in the migration mechanism of a wide lines of a top level interconnect of a standard metallization. The study demonstrates the differences of the transferred metallization system and the influence for the degradation behaviour and reliability.


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Published: November 2008

Wafer Level Reliability Gate Oxide Integrity tests such as voltage-ramped and constant current stress have been conducted on area plate-type, poly edge and STI edge intensive test structures. The WLR tests are required for qualifying the process of integrating 3.3 nm and 12.5 nm dual gate oxide operated under the bias of 1.8V and 5V respectively on a single chip.


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Published: November 2008

Several methods have been investigated for gettering impurities during CMOS processing, in order to achieve high-quality oxides on thick SOI. The use of buried implants, buried polysilicon, surface implants, and isolation trenches was found to significantly improve the oxide quality in each case


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Published: July 2008

With the further scaling down of CMOS devices, hot carrier induced degradation has become one of the most important reliability concerns. In the hot carrier effect, carriers are accelerated by the channel electric fields and become trapped in the oxide. These trapped charges cause time dependent shifts in measured device parameters.


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Published: July 2008

Hot carriers, the high kinetic energy carriers due to high electric field in the channel region, are injected into the gate oxide and form interface states, which in turns causes degradation of MOS device performance. The hot carrier effect has become more severe as the device size continues to scale down to submicron range. This aging phenomenon that threatens the circuit and product lifetimes warrants it to be considered as the key challenge in reliability.


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