104 entries, filtered by: Paper
Published: March 2010

For the first time, this paper demonstrates the experimental results for two types of test structures of field transistors up to 200°C. The field transistor structures which are stripe (conventional) and square ring (new) structures were measured and investigated in term of field leakage current and onstate characterization at high temperature.


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Published: March 2010

Sub-wavelength structures in metal films have interesting optical properties that can be implemented for sensing applications: gratings act as wire grid polarizer, hole arrays with enhanced transmission can be used as spectral filters. This paper demonstrates the feasibility of these nanostructures using 180 nm and 90 nm complementary metal-oxide semiconductor (CMOS) processes. The metal layers of the process can be used for optical nanostructures with feature sizes down to 100 nm.


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Published: October 2009

In this paper we describe a novel tool for modeling the fabrication of MEMS and semiconductor devices, and show some examples of its application in the MEMS foundry business. The tool allows an accurate visualization of the step-by-step crreation of the final 3-D device geometry by using the 2-D layout and a description of the fabrication process.


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Published: August 2009

One time programmable (OTP) electrically programmed read only memory (EPROM) become a simple low cost solution in non-volatile memory (NVM) to be integrated in variety of CMOS baseline technology node platforms without extra masks or additional process cost incur. The feasibility of EPROM floating gate built on buried channel pMOSFET was explored experimentally. The buried channel device physic fundamental characteristics would lead to consistently high erased cell current (Ioff) in μA level instead of expected pA level for EPROM cell in erased state. Alternative external voltage biasing could not be applied due to unavailability of floating gate terminal connection to control the buried channel onoff state.


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Published: August 2009

OLED-on-CMOS micro-displays are widely studied in the recent years due to the fast development of OLED. However, there are some challenges to fabricate the electrodes of OLED. In this study, the process challenges are discussed, and the surface roughness is suggested to be one of the critical parameters.


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Published: August 2009

Resistance of contacts on nonsalicided active must be sufficiently low in order for a device to function. The objective of the work presented here is to discuss steps taken to reduce initially high contact resistance on non-salicided active of a high breakdown voltage transistor to meet functional requirement. In order to create a special 30V high voltage transistor in a NAND flash device, the active region between gate and junction has to be non-salicided. Therefore, the contact resistance needs to be lowered down by other means. This paper shows substantially reduction in contact resistance value and better resistance distribution uniformity across a wafer through a combination of plug implant and improved contact etching with O2 flush condition and additional oxide etching.


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Published: August 2009

This study was carried out to investigate the bimodal distribution of Vt (threshold voltage) of 3.3V differential pair PMOS structure within a wafer in which the abnormal transistor shows half lower than normal threshold voltage value and higher off state leakage current. The root cause was identified by simulation which is increasing gate oxide thickness of thin gate oxide area and finally matches behavior of the abnormal transistor with low threshold voltage and high off state leakage. The solution was implemented with O2 descum process into the dual gate oxide process flow, which O2 descum process was inserted after photo resist patterning for thick gate oxide in order to remove potential thin photo resist scum which is blocking wet etch reaction to oxide and causes thick gate oxide to remain at the thin gate oxide area. Details evaluation, measurement and result will be further discussed.


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Published: August 2009

In SOC (System on Chip) technology, the various types of devices located on an IC chip typically have different operating voltages thus requiring multiple gate oxide layers of different thickness to be formed. In order to form different gate oxide, several oxide removal and growth steps have to be carried out which make the process more complex and particularly have a detrimental impact on the Shallow Trench Isolation (STI) structures.


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Published: August 2009

Monolithically integrated photodiodes with high spectral responsivity over the entire visible and the near infrared spectral range are of growing interest for the semiconductor industry, since the next generation of optical data storage devices (Blue DVD) will soon be brought to market. In this paper, the bandwidth of photodiode dependence on the junction implant conditions and thermal budget was simulated by TCAD. It shows significant dependence on these process conditions. The corresponding mechanism related to RC delay, relationship between depletion region and light absorption will be discussed in detail with the help of simulation pictures and simple model explanation.


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Published: July 2009

This paper presents an investigation of low oxide breakdown voltage on polysilicon-oxide-diffusion (POD) capacitor. The dielectric was 7 nm thermal oxide which was grown simultaneously for MOS transistor as gate oxide. The V-Ramp measurement showed bimodal distribution of Vbd with one circular patch having < 7 V instead of the target Vbd (10 V). The size of the patch depends on the POD capacitor area. This behavior was not observed on gate oxide of MOS transistor and 22.5 nm POD capacitor. Process partition check, including wafer orientation and wafer slot arrangement was conducted. The specific process step causing the patch signature has been identified successfully.


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