104 entries, filtered by: Paper
Published: May 2011

In this paper we present a modular trench isolated high voltage SOI process with the possibility to integrate various types of high voltage transistors. The integration of these additional 650 V devices takes place in a modular approach which allows a high process flexibility to support different applications with a minimum number of additional or changed process steps.


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Published: April 2011

Silicon photodiode integrated with CMOS has been in extensive study for the past ten years due to its wide use in applications such as short-distance communication, VCD players, ambient light sensors and many other intelligent systems. In recent years, high speed blue-ray DVD is replacing conventional DVD due to its larger storage capacity and higher speed. In this work, the photodiode optimized for blue ray is fully integrated with standard 0.35um CMOS process and the bandwidth dependency upon thermal process and epitaxial material is investigated.


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Published: March 2011

A study has been carried out to improve metal-insulator-metal (MIM) capacitor's capacitance density and linearity performance. The scopes of the study included single MiM and stack MIM structures. Different dielectric schemes were evaluated with their corresponding capacitance density, breakdown voltages and linearity coefficient to voltage and temperature variation etc. characterised.


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Published: March 2011

Drastically device dimension shrinkage and rigorous requirement in automotive era puts Negative Bias Temperature Instability (NBTI) at the forefront of reliability issue recently. The PMOS parametric degradation during negative bias high temperature aging can depend on many process variables of the manufacturing flow. A study was carried out to explore the process related dependencies for high voltage PMOS transistor and to increase the device robustness against NBTI stress. In this papers, the process impact on the NBTI degradation were discussed. This investigation work provides methods for significant suppression of the NBTI degradation with silicon rich oxide (SRO) inter layer dielectric (ILD) liner and two-step gate oxidation.


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Published: January 2011

Visualization is still the most important tool in medical diagnostics to allow for the physician, in combination with their medical knowledge, to detect diseases within the human body and choose healing treatments in order to enable recovery. For minimal invasive surgical operations that use endoscopic tools, imaging camera modules that have both a small volume and a good resolution are necessary to ensure the success of the surgical treatment.
Microsystem technologies now allow for the direct integration of imaging optics and sensors in a system.


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Published: January 2011

Miniaturized video endoscopes with an imager located at the distal end and a simplified opto-mechanical layout are presented. They are based on a CMOS imager with 650 x 650 pixels of 2.8 μm pitch and provide straight view with 75° and 110° field of view at f/4.3. They have an outer diameter of 3 mm including the shell and a length of approx. 8 mm. The optics consist of polymer lenses in combination with a GRIN and a dispensed lens. Using a simple flip chip assembly, optical axis alignment better than 10 μm and a contrast of 30 % at 90 LP/mm was achieved. The 75° FOV system was sealed at the front window using a solderjetting technology, providing 10-9 mbar*l/s leakage rates even after several autoclave cycles.


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Published: November 2010

This paper suggests an improved method to round off the concave corners of the deep trenches formed by plasma etch. The corner rounding technique, sacrificial oxidation (SACOX) before gate oxidation, has been practiced on the shallow trench isolation (STI) to improve the CMOS leakage performance.


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Published: July 2010

A novel 0.18μm 200V integrated technology based on Partial SOI and lateral Super Junctions devices is presented. The dielectric isolation inherent in SOI allows simple and areaefficient integration of electrically floating CMOS and HV devices while removing all substrate carrier injection-related parasitic effects. The Super Junctions give a competitively low on-resistance of HVMOS and provide a wide-range breakdown voltage-scaling capability.


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Published: April 2010

The high voltage device can be embedded into conventional shallow trench isolation (STI) logic process. Basically, SVX (Smart Voltage Extension) technique was applied in order to integrate 32V high voltage LDMOS into a standard 0.18 micron low voltage CMOS technology without any process change. However, a double hump issue was being observed in high voltage LDNMOS. The double hump phenomenon is mainly occurs due to lower threshold voltage of transistor corner that will lead to high sub-threshold leakage. This paper presents a solution by applying boron implant in HV LDNMOS to suppress the double hump issue. The retrograde baseline CMOS p-well implant is used for this purpose to avoid an additional mask and process step.


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Published: April 2010

An experiment in base and pedestal collector implant has been conducted to study the impact and further improve the performance of a 0.6 micron silicon poly emitter bipolar transistor. It has been shown the bandwidth can be improved form 13GHz to 15GHz with acceptable changes to the other bipolar performances.


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