33 entries, filtered by: More than Moore
Published: August 2009

One time programmable (OTP) electrically programmed read only memory (EPROM) become a simple low cost solution in non-volatile memory (NVM) to be integrated in variety of CMOS baseline technology node platforms without extra masks or additional process cost incur. The feasibility of EPROM floating gate built on buried channel pMOSFET was explored experimentally. The buried channel device physic fundamental characteristics would lead to consistently high erased cell current (Ioff) in μA level instead of expected pA level for EPROM cell in erased state. Alternative external voltage biasing could not be applied due to unavailability of floating gate terminal connection to control the buried channel onoff state.


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Published: August 2009

OLED-on-CMOS micro-displays are widely studied in the recent years due to the fast development of OLED. However, there are some challenges to fabricate the electrodes of OLED. In this study, the process challenges are discussed, and the surface roughness is suggested to be one of the critical parameters.


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Published: July 2008

In 0.11um and larger technology node non-volatile memory process integration, undesired cobalt salicide residue formation is found to degrade ohmic contact resistant and cause severe yield loss. TiN/Ti/Co stack is applied in the process to get good CoSi2 formation. The abnormal salicide residue formation is detected after cobalt stripping process which is applying a two step selective wet etching.


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Published: October 2006

Wafer bonding is an essential process step in the development and production of MEMS devices because it allows the possibility of realizing real three dimensional structures, such as functional capping of free movable structures. Because this process step is so important, it has to fit suitably into an industrial wafer-processing flow, so that wafer bonding can be performed very reproducibly with high process stability and at low cost.


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Published: September 2006

An infrared focal plane array with 16 x 8 pixels is presented. The not-cooled thermopile sensor array has been completely fabricated in CMOS technology. The main field of application of this sensor is to detect the presence of persons in buildings by their own thermal radiation. For a wide spread use of this sensor a low cost production with established CMOS technologies is necessary. The chip embraces the sensor pixels and highly integrated electronic circuits to allow a simple sensor interfacing.


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Published: June 2006

An original work in developing technology that allows the integration of multiple vertical power devices within Power ICs has been presented in this manuscript. The developed technology uses a combination of top and back trenches as well as wafer sawing to achieve complete dielectric isolation between the silicon islands. Each silicon island is capable of holding either single vertical power device or CMOS circuitry. The test structures have been manufactured, wafer diced and individual chips packaged and tested initially for mechanical and thermal stability.


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Published: March 2006

The feasibility of EEPROM memories in SOI process technologies has been proven. It has also been shown that known data retention problems at high temperatures caused by leakage currents can be solved without extra circuitry. In this paper results of EEPROM cell matrix measurements regarding functionality and reliability will be presented. Different cell designs will be compared. Furthermore, a 32x16 bit EEPROM prototype and memory test results will be shown.


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Published: October 2005

In this paper a non-destructive test structure for monitoring the strength of anodic bonded glass silicon wafer compounds is introduced. The realisation of the structure, the calculation of the surface energy using FEM and practical results are shown.


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Published: May 2004

This paper reports on glass frit wafer bonding, which is a universally usable technology for wafer level encapsulation and packaging. After explaining the principle and the process flow of glass frit bonding, experimental results are shown. Glass frit bonding technology enables bonding of surface materials commonly used in MEMS technology. It allows hermetic sealing and a high process yield. Metal lead throughs at the bond interface are possible, because of the planarizing glass interlayer. Examples of surface micromachined sensors demonstrate the potential of glass–frit bonding.


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Published: October 2003

The importance of surface micromachining processes has increased over the last few years. After the fundamental problems of these technologies have been solved in research institutes, surface micromachined components now arrive in industrial production, e.g. inertial sensors for automotive applications. In comparison to the classical bulk micromachined components, technologies based on surface micromachining provide a wide range of advantages.


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