36 entries, filtered by: High-Voltage
Published: July 2008

In this paper, a 40V versatile HV LDMOS technology with lower Rdson has been developed in the existing 0.18μm LV CMOS process. The HV LDMOS are designed by using DOE concept on the simulation results from T-supreme followed by Medici.


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Published: May 2008

The snapback trigger voltage of the NDMOS in a 0.18μm automotive smart power technology is strongly reduced at large gate bias. This behavior of the deep-submicron multiresurf NDMOS, which makes its ESD protection difficult and limits its electrical safe operating area, and the influence of various device modifications are investigated by TCAD simulation. SCR-based ESD protection schemes for I/O and power supply protection are presented. For supply protection the SCR is modified to increase its holding voltage. The ability to protect the NDMOS at non-zero gate bias is discussed.


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Published: December 2007

To fulfill the current market demand of smart power IC’s an attempt was made to incorporate the high voltage devices in the current baseline of 0.18 micron low voltage process. Circular high voltage structure proposes for some advantages such as higher breakdown voltage, lower leakage current, less area and etc over the normal structure. The NMOS & PMOS both types of transistors are optimized in terms of their structure and process condition to achieve large breakdown voltage with lower Ron value.


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Published: June 2006

High voltage mos transistors usually have a drift zone in the drain region. The conductivity of this drift zone is strongly dependent on the flowing current and gate voltage. Thus it has generally to be modelled with a variable resistance representing the effects on the current. The goal of this work is to show a phenomenological macro model including AC modelling. The model is restricted to a lumped element sub-circuit, which can be processed by a standard spice simulator.


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Published: May 2005

This work describes the electrical performance of a high voltage deep trench isolation on SOI wafers. Several process and design related effects on the electrical isolation capability are investigated. Several process parameters during the trench process are examined with regard to isolation capability as well as defect generation. Trench edge geometry and layout have also a very strong impact on the isolation capability.


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Published: April 2002

The adjustment of emitter efficiency by variation of doping profiles or application of lifetime control techniques such as irradiation of electrons and helium are two generally recognized concepts for the improvement of power device characteristics. In this work both concepts were studied by use of device simulation for the development of an IGBT and freewheeling diode chipset for 3.3kV.


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