36 entries, filtered by: High-Voltage
Published: June 2012

This paper demonstrates and discusses novel “three dimensional” silicon based junction isolation/termination solutions suitable for high density ultra-low-resistance Lateral Super-Junction structures.


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Published: June 2012

The XU035 series is X-FAB’s 0.35-micrometer Modular 700V Ultra-High-Voltage (UHV) Technology. Based upon the standard 1P3M process with single 5V gate oxide, 0.35-micron drawn gate length and metal design rules, the platform is engineered for applications needing an integrated power and startup device solution.


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Published: May 2012

Overwhelmed by the complexity of 700V designs due to cross talk, ESD, reliability or latch-up issues? Are your design challenges compounded by chip size and time-to-market issues? This webinar showcases X-FAB's new CMOS-based process for ultra-high-voltage apps such as AC LED lighting, ultra-low standby/no-load power and other power conversion and control applications. The combination of this cost-competitive process architecture and X-FAB’s design support enables first-time-right/first time functional designs for high-voltage lighting and power supply applications


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Published: May 2012

XDM10 is X-Fab´s dielectric trench insulated smart power technology. Main target applications are analog switch ICs, driver ICs for capacitive, inductive and resistive loads and EL / piezo driver ICs for applications using 110V net supply. The typical breakdown voltage of the HV-DMOS devices is >350 V or >275V. The modular process combines DMOS, bipolar and CMOS processing steps that are compatible with dielectric insulation to provide a wide variety of MOS and bipolar devices with different voltage levels within a dielectric bi-directional high voltage trench insulation on the same die.


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Published: April 2012

The huge demand for high voltage, high current power devices on Silicon on Chip (SoC) has led to the development of Lateral IGBT (LIGBT), touted as the best candidate to serve these two purposes. This paper is the first to review the research works on LIGBTs published till now. The LIGBTs are categorized into four types based on different technologies applied, mainly Junction Isolation (JI), Silicon On Insulator (SOI), Partial SOI (PSOI) and Membrane, and ten varieties based on their device mechanisms, such as Reverse Conducting, Trench Gate and Super Junction.


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Published: March 2012

Electrostatic discharge (ESD) is a serious threat to integrated circuits (ICs) that can cause irreversible damage. This webinar on ESD protection will show you solutions on how to eliminate ESD threats in complex analog/mixed-signal and high-voltage designs. It covers an overview of various ESD protection concepts, and explains the structures and schemes available to protect against electrostatic discharge in X-FAB’s enhanced 0.35 and 0.18 micrometer XH035 and XH018 high-voltage foundry processes. The webinar presentation also highlights similarities and differences among ESD protection concepts, outlining the advantages and disadvantages of each in circuit designs.


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Published: November 2011

The power semiconductor industry has grown steadily in past two decades from $2.7 billion in 1992 and is expected to reach $13.1 billion in annual sales volume this year due to rapid proliferation of power electronics in many fields like telecommunication, automotive, new renewable energy system and energy conversion application. Among power transistor products, sales of modules built with Insulated Gate Bipolar Transistor (IGBT) are expected to increase 10 percent to $2.5 billion this year.
This paper gives an overview to different types of IGBTs available in current market as well as those under development.


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Published: September 2011

Using a trench isolated 650V quasi-vertical n-channel DMOS as a starting point several new 650V transistor types have been evaluated. Mainly by design measures a 650V depletion DMOS, a 650V PMOS and a 650V IGBT were created for a modular integration into the process flow.


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Published: May 2011

This paper demonstrates and explains the effects of hot carrier injection and interface charge trapping correlated with impact ionization under normal on-state conditions in a highly dense low-resistance Super-Junction LDMOSFET. The study is done through extensive experimental measurements and numerical simulations using advanced trap models.


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Published: May 2011

Successful integration of 100V LDMOS devices in 0.35μm CMOS technology is presented in this paper. These integrated devices are enhanced N-type and P-type LDMOS which are compatible with thin (14nm) and thick (40nm) layers of gate oxide. A breakdown voltage of more than 100V with RDS (ON) =200/180mΩ.mm2 for N-type LDMOS and RDS (ON) =690/640mΩ.mm2 for P-type LDMOS with 14nm/40nm gate oxide thickness.


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