40 entries, filtered by: High-Voltage
Published: March 2015

For gate driver ICs in three phase power applications level shifters with more than 900V operating voltage are required. The extension of the voltage rating of an existing trench isolated SOI process was done with different device concepts: Serial stacking of lower voltage devices was evaluated as an alternative approach to conventional quasi-vertical and charge compensated lateral devices which need layout and material modifications. 


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Published: August 2014

Serial stacking of high voltage devices in a SOI process to achieve higher operating voltages is an alternative approach to layout and material modifications being necessary in a conventional quasi-vertical approach. Based on a sufficient 900 V trench isolation the stacking was first tested with existing lower voltage diodes and compared to new 900 V diodes with the conventional quasi-vertical construction.


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Published: July 2013

For most devices sitting on SOI wafer, there is a consideration of backside coupling effect. This phenomenon becomes catastrophic if the device sits on the SOI wafer is an IGBT which consists n-p-n-p structure and employs both the partial SOI and DTI technique. Earlier leakage had been found during development of 200V superjunction lateral IGBT (SJ LIGBT) on partial SOI.


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Published: July 2013

XDH10 is X-Fab´s dielectric trench insulated smart power technology. Main target applications are analog switch ICs, driver ICs for capacitive, inductive and resistive loads and EL / piezo driver ICs for applications using 220V net supply. The typical breakdown voltage of the HV DMOS devices is >350V or >650V. The modular process combines DMOS, bipolar and CMOS processing steps that are compatible with dielectric insulation to provide a wide variety of MOS and bipolar devices with different voltage levels within a dielectric bi-directional high voltage trench insulation on the same die.


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Published: May 2013

This paper demonstrates a novel lateral superjunction (SJ) lateral insulated gate bipolar transistor (LIGBT) fabricated in 0.18μm partial silicon on insulator (PSOI) HV process. The results presented are based on extensive experimental measurements and numerical simulations.


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Published: May 2013

This paper presents versatile HV lateral JFET design method on 0.18μm SOI BCD technology to achieve variable Vth(pinch-off voltage) and Idsat, without DIBL effect over full operating Vds range and scalable breakdown voltage capability on both N-ch and P-ch JFET. The significant advantage of a HV JFET compared to depletion MOSFET is the lower area consumption in real circuit design which due to higher Idsat values at Vgs=0V.


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Published: May 2013

The XP018 series is X-FAB’s 0.18 micron Modular Mixed Signal CMOS High Performance Analog Mixed-Signal Technology. Based upon the industrial standard single poly with up to six metal layers 0.18-micron drawn gate length N-well process, integrated with high voltage and Non-Volatile-Memory modules, the platform is engineered for applications needing an integrated solution and cost efficient process for high performance analog ICs. Targeted applications are switching applications, lighting, display, etc; operating in temperature range of -40 to 175 °C.


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Published: January 2013

The XT018 series is X-FAB’s 0.18 micron Modular High-voltage SOI CMOS Technology. Based on SOI wafers and the industrial standard single poly with up to six metal layers 0.18-micron drawn gate length process, integrated with high voltage and Non-Volatile-Memory modules, the platform is specifically designed for a new generation of cost-effective "Super Smart Power" technology; operating in temperature range of -40 to 175 °C.


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Published: January 2013

Classical high voltage devices fabricated on SOI substrates suffer from backside coupling effect which could result in premature breakdown. This phenomenon becomes more prominent if the structure is an IGBT which features a p-type injector. To suppress the premature breakdown due to crowding of electro-potential lines within a confined SOI/buried oxide structure, the partial SOI (PSOI) technique is being introduced. This paper analyzes and characterizes the off-state behaviour of an n-type Superjunction (SJ) LIGBT fabricated on PSOI substrates.


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Published: December 2012

This paper evaluates the technique used to improve the latching characteristics of the 200V n-type superjunction (SJ) LIGBT on partial SOI. The initial design latches at about 23V with forward voltage drop (VON) of 2V at 300A/cm2. The latest design shows increase of latch-up voltage close to 100V without significant expense of VON.


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