28 entries, filtered by: Characterization
Published: May 2011

Successful integration of 100V LDMOS devices in 0.35μm CMOS technology is presented in this paper. These integrated devices are enhanced N-type and P-type LDMOS which are compatible with thin (14nm) and thick (40nm) layers of gate oxide. A breakdown voltage of more than 100V with RDS (ON) =200/180mΩ.mm2 for N-type LDMOS and RDS (ON) =690/640mΩ.mm2 for P-type LDMOS with 14nm/40nm gate oxide thickness.


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Published: March 2011

A study has been carried out to improve metal-insulator-metal (MIM) capacitor's capacitance density and linearity performance. The scopes of the study included single MiM and stack MIM structures. Different dielectric schemes were evaluated with their corresponding capacitance density, breakdown voltages and linearity coefficient to voltage and temperature variation etc. characterised.


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Published: March 2010

For the first time, this paper demonstrates the experimental results for two types of test structures of field transistors up to 200°C. The field transistor structures which are stripe (conventional) and square ring (new) structures were measured and investigated in term of field leakage current and onstate characterization at high temperature.


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Published: August 2009

One time programmable (OTP) electrically programmed read only memory (EPROM) become a simple low cost solution in non-volatile memory (NVM) to be integrated in variety of CMOS baseline technology node platforms without extra masks or additional process cost incur. The feasibility of EPROM floating gate built on buried channel pMOSFET was explored experimentally. The buried channel device physic fundamental characteristics would lead to consistently high erased cell current (Ioff) in μA level instead of expected pA level for EPROM cell in erased state. Alternative external voltage biasing could not be applied due to unavailability of floating gate terminal connection to control the buried channel onoff state.


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Published: August 2009

This study was carried out to investigate the bimodal distribution of Vt (threshold voltage) of 3.3V differential pair PMOS structure within a wafer in which the abnormal transistor shows half lower than normal threshold voltage value and higher off state leakage current. The root cause was identified by simulation which is increasing gate oxide thickness of thin gate oxide area and finally matches behavior of the abnormal transistor with low threshold voltage and high off state leakage. The solution was implemented with O2 descum process into the dual gate oxide process flow, which O2 descum process was inserted after photo resist patterning for thick gate oxide in order to remove potential thin photo resist scum which is blocking wet etch reaction to oxide and causes thick gate oxide to remain at the thin gate oxide area. Details evaluation, measurement and result will be further discussed.


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Published: August 2009

Monolithically integrated photodiodes with high spectral responsivity over the entire visible and the near infrared spectral range are of growing interest for the semiconductor industry, since the next generation of optical data storage devices (Blue DVD) will soon be brought to market. In this paper, the bandwidth of photodiode dependence on the junction implant conditions and thermal budget was simulated by TCAD. It shows significant dependence on these process conditions. The corresponding mechanism related to RC delay, relationship between depletion region and light absorption will be discussed in detail with the help of simulation pictures and simple model explanation.


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Published: May 2008

The long term isolation properties of deep trenches in thick SOI have been investigated by current-voltage characteristics. A strong change of the measured trench leakage current was observed depending on the applied voltage. Further on a marked decrease of the leakage current was observed depending on the duration and polarity of the applied stress.


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Published: December 2007

Ultra low leakage is considered as a major requirement for most of the common device performance. Larger circuit design size, device threshold voltage scaling, and device dimension shrinkage are causing this dramatically increase in leakage current. This significant increment of leakage with each technology generation warrants that it to be considered as the key challenge in IC design.


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Published: May 2007

A new smart power SOC IC process including up to 50V HV-MOS transistors, SONOS principle based non-volatile memory components and analog devices using an advanced 0.18μm platform is presented. Process architecture and device portfolio are focused on automotive applications e.g. sensor signal conditioning and integrated output drivers. HV-MOS and SONOS integration as well as device properties are discussed with regard to reliability aspects. Additionally key features of NPN bipolar transistors and depletion NMOST are given.


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Published: March 2007

MEMS, such as surface micromachined inertial sensors, require cap wafer bonding to protect the sensitive structures at the wafer level against mechanical damage and environmental influences, in order to allow the finalization of the wafer processing, dicing and packaging. In most cases, the cap is solely for mechanical protection without any electrical function, because standard wafer bonding processes cannot provide the possibility of local electrical contacts from system to cap wafer (glass frit, adhesive and low temperature direct bonding are nonconductive, while the metal interlayer bonding bond frame is a large, dominating contact area).


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