23 entries, filtered by: Wafer Manufacturing
Published: September 2011

IC content in cars has been growing exponentially, adding significant complexity to automotive chip design and manufacturing. Today’s cars feature many semiconductor applications such as tire pressure monitoring sensors and accelerometers for airbag systems. Add electronic components to improve engine performance, increase fuel efficiency, control modern entertainment and communications devices, provide Internet capability and handle new comfort functions... Now add the challenge of making the associated ICs survive for many years in extreme heat and cold, rain and snow, salt, g-forces, humidity, dry and dusty conditions...and you’ve got your hands full designing for one of the most harsh IC operating environments. 


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Published: March 2011

Reliability is a critical performance factor for semiconductor technologies. This webinar describes the physical phenomena that can lead to device degradation during circuit operation, and deduces reliability models for CMOS technologies. These models can be used for design optimization (“Design for Reliability”) to enable very robust products, and for reliability risk assessment for advanced operating conditions such as high temperature and high voltage.


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Published: November 2010

This paper suggests an improved method to round off the concave corners of the deep trenches formed by plasma etch. The corner rounding technique, sacrificial oxidation (SACOX) before gate oxidation, has been practiced on the shallow trench isolation (STI) to improve the CMOS leakage performance.


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Published: April 2010

The integration of full custom analog circuitry into a silicon chip, to provide cost-effective products, requires a full understanding of the process architecture and uses completely different methods compared with those used for digital designs. This webinar briefly covers the digital design arena before entering into in-depth discussion of analog layout techniques. It explores the integration of X-FAB-supported primitive devices into complex integrated chips in detail, including diffusions, wells and associated layers that can be merged. The session also covers derivation of "well" combinations from the design layers, and gives guidelines for high-voltage interconnects across these well regions to avoid parasitic leakage paths.


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Published: July 2009

This paper presents an investigation of low oxide breakdown voltage on polysilicon-oxide-diffusion (POD) capacitor. The dielectric was 7 nm thermal oxide which was grown simultaneously for MOS transistor as gate oxide. The V-Ramp measurement showed bimodal distribution of Vbd with one circular patch having < 7 V instead of the target Vbd (10 V). The size of the patch depends on the POD capacitor area. This behavior was not observed on gate oxide of MOS transistor and 22.5 nm POD capacitor. Process partition check, including wafer orientation and wafer slot arrangement was conducted. The specific process step causing the patch signature has been identified successfully.


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Published: February 2009

This opinion piece analyzes the dire dilemma many IDMs face today, explains typical symptoms and reactions, and shows possible strategies out of a death spiral. It highlights why consolidation is inevitable for many players, and how pro-active consolidation can increase the number of options available and help IDMs avoid falling into the “too little too late” trap. Specifically, it covers: Current economic conditions and consequences for IDMs; Implications of competitive and financial pressure faced by IDMs; Consolidation and other strategic options, and their implementation; Risks of waiting too long; Potential role of foundries in consolidation and moving forward.


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Published: November 2008

Traditional cross-sectional sample treatment methods such as BOE (Buffered oxide etch), can easily highlight Titanium Salicide (TiSi2) by etching away the TiSi2 (thus creating voids or cavitations) with no impact on the silicon underneath the salicide. However, this method does not work for devices using Cobalt Salicide (CoSi2) technology. The work presented here is to introduce a special etchant or chemical mix that will etch the Cobalt Salicide (CoSi2), with no significant impact on the silicon underneath the salicide layer.


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Published: November 2008

The fast scanning mechanism of High Current batch Implanter is achieved by spinning the wafer disk with angular speed more than 1200 Rotation-Per-Minute (RPM). If particles hit device wafers during implant it can cause serious damage to device structure. Particle generation areas are mainly from Source terminal, Accelerator Column, Plasma Flood Gun (PFG) and beam line wall.


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Published: September 2007

Using silicon-based MEMS technologies, the cost-efficient production of gyroscopes has become possible in recent years. As a result, gyroscopes are entering new markets, such as for highly accurate GPS-Instruments where the gyroscope enhances accuracy in situations where satellite reception is lost, for example in tunnels. However, since all gyroscopes are very precise resonating measurement devices, this leads to stringent wafer processing requirements for their production.


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Published: October 2006

Conventional I-line lithography process utilizes single post-apply bake temperature to unify and simplify the process. As design rule shrinks and mask field size increases, tighter specification is applied on non-critical implant layers, including thick implant resist with thickness typically 4.0 mum and above. Poor uniformity for CD & overlay was observed for thick implant resist layer. Systematic uncorrectable overlay residue was observed from the overlay map.


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