37 entries, filtered by: Reliability
Published: May 2008

The long term isolation properties of deep trenches in thick SOI have been investigated by current-voltage characteristics. A strong change of the measured trench leakage current was observed depending on the applied voltage. Further on a marked decrease of the leakage current was observed depending on the duration and polarity of the applied stress.


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Published: December 2007

Ultra low power device requires extremely low level of CMOS standby current leakage. At 0.15um geometric technology, wafer edge leakage current is more severe yield issue and it was suspected from inter metal dielectric thickness and contact module process uniformity. Investigation has been made and our studies have been carried out on process optimization of contact module which are including contact etch tools performance, contact stopper materials, thickness and contact etch time. By implementing the optimized condition, we are able to reduce standby leakage current on wafer edge dice about 5 times reduction.


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Published: December 2007

Today three different main failure mechanisms in metallization are well known. Defect behaviour in reliability stress tests of metallization are influenced by electromigration (current), stress migration (mechanical) and thermomigration (temperature) effects. In this study, stress migration effects were evaluated using high temperature storage test and resistance measurements over time.


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Published: December 2007

Ultra low leakage is considered as a major requirement for most of the common device performance. Larger circuit design size, device threshold voltage scaling, and device dimension shrinkage are causing this dramatically increase in leakage current. This significant increment of leakage with each technology generation warrants that it to be considered as the key challenge in IC design.


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Published: April 2006

In the paper new testing methods for MEMS will be presented that can be applied on wafer level in early stage of the manufacturing process. First measurements of the eigenfrequencies test specimen were done. A Finite Element model was created to determine the plate thickness for the measured eigenfrequencies. There is a good agreement between the microscopic determined real thicknesses and the calculated thicknesses. Also a stochastic model was created to describe the influence of different parameters on the calculated thickness of membrane.


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Published: March 2006

The feasibility of EEPROM memories in SOI process technologies has been proven. It has also been shown that known data retention problems at high temperatures caused by leakage currents can be solved without extra circuitry. In this paper results of EEPROM cell matrix measurements regarding functionality and reliability will be presented. Different cell designs will be compared. Furthermore, a 32x16 bit EEPROM prototype and memory test results will be shown.


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Published: October 2005

In this paper a non-destructive test structure for monitoring the strength of anodic bonded glass silicon wafer compounds is introduced. The realisation of the structure, the calculation of the surface energy using FEM and practical results are shown.


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