34 entries, filtered by: Reliability
Published: September 2011

A study on the effect of process fabrication for MIM capacitors analog matching performance was carried out, impacts from the MIM dielectrics, capacitor top and bottom metal materials, capacitor metal etch, wet cleaning, annealing process will be revealed by comparing the Pelgrom coefficients, i.e. the dependence of difference in capacitance of the matching pairs with respect to their corresponding square root of capacitor areas, the smaller the difference the better the matching.


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Published: September 2011

This paper presents a simple but effective way to improve an NMOS transistor’s ESD robustness for use in I/O pads. Simulation and physical failure analysis has been performed to identify the source of the ESD failure. Process splits have been performed primarily at LDD (Lightly Doped Drain) implant and salicidation process based on data presented in this paper.


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Published: July 2011

Are you looking for a highly reliable embedded non-volatile memory (NVM) solution in an advanced technology node that is easy to integrate into your design? One that can serve as a platform for developing complete product families? This free webinar introduces X-FAB’s new XH018 eFlash option – the industry’s most cost-effective combination of high voltage and embedded flash for complex SoCs. Find out how it works and why eFlash is ideally suited for for high-speed microcontroller, digital power and automotive applications.


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Published: May 2011

This paper demonstrates and explains the effects of hot carrier injection and interface charge trapping correlated with impact ionization under normal on-state conditions in a highly dense low-resistance Super-Junction LDMOSFET. The study is done through extensive experimental measurements and numerical simulations using advanced trap models.


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Published: March 2011

Drastically device dimension shrinkage and rigorous requirement in automotive era puts Negative Bias Temperature Instability (NBTI) at the forefront of reliability issue recently. The PMOS parametric degradation during negative bias high temperature aging can depend on many process variables of the manufacturing flow. A study was carried out to explore the process related dependencies for high voltage PMOS transistor and to increase the device robustness against NBTI stress. In this papers, the process impact on the NBTI degradation were discussed. This investigation work provides methods for significant suppression of the NBTI degradation with silicon rich oxide (SRO) inter layer dielectric (ILD) liner and two-step gate oxidation.


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Published: March 2011

Reliability is a critical performance factor for semiconductor technologies. This webinar describes the physical phenomena that can lead to device degradation during circuit operation, and deduces reliability models for CMOS technologies. These models can be used for design optimization (“Design for Reliability”) to enable very robust products, and for reliability risk assessment for advanced operating conditions such as high temperature and high voltage.


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Published: November 2009

Long-term functionality of integrated circuits (ICs) is based on the reliable operation of each component. Semiconductor device reliability within an IC is dependent on the specific stress mission profile of the ICs' intended application and its operating conditions. Shrinking primitive device dimensions and extended operating conditions compound the environmental challenges that designers face in trying to predict chip reliability.


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Published: October 2009

At high temperature, designers are faced with additional technological and design challenges. These issues and how to address them are discussed in this presentation. The webinar looks at X-FAB's high temperature solutions, in particular its latest High Temperature Modular CMOS process (XA035), a comprehensive CMOS offering with High Voltage (HV), RF, and EEPROM integration that is suitable for temperatures up to 175C. The presentation also covers high temperature modelling, application specific reliability and design for reliability.


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Published: July 2009

This paper presents an investigation of low oxide breakdown voltage on polysilicon-oxide-diffusion (POD) capacitor. The dielectric was 7 nm thermal oxide which was grown simultaneously for MOS transistor as gate oxide. The V-Ramp measurement showed bimodal distribution of Vbd with one circular patch having < 7 V instead of the target Vbd (10 V). The size of the patch depends on the POD capacitor area. This behavior was not observed on gate oxide of MOS transistor and 22.5 nm POD capacitor. Process partition check, including wafer orientation and wafer slot arrangement was conducted. The specific process step causing the patch signature has been identified successfully.


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Published: November 2008

The work presented here shows a series of engineering runs to improve the AC HCI lifetime for a 0.60μm NMOS. The conventional method of increasing NLDD energy and reducing NLDD dose did not achieve significant improvement. The study concludes that tilting the NLDD implant, coupled with prolonging the NLDD anneal and increasing the Poly CD can improve the lifetime significantly. A short HCI test was performed to compare the response of different splits.


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