Greater Challenges with Process Characterization and Design Support
The digital world essentially relies on two basic devices, NMOS and PMOS transistors. From the design perspective, devising digital ICs is rather straightforward. The process is largely removed from both technology considerations and the actual physics of the devices because electronic systems are modeled using hardware description language (HDL). In addition, place-and-route tasks and verification are highly automated. Digital IC design typically is focused on logic correctness, maximizing circuit density, and placing circuits so clock and timing signals are routed efficiently. As a highly automated process – at least for technologies above 90-nanometer – it leads to variable, fab-independent netlists and easily generated layouts that usually are right the first time.
In contrast to digital design – in which only a few device parameters such as threshold voltage, leakage and saturation currents need to be considered – analog/mixed-signal design must cope with far more complex specifications. The physics of the devices are a primary concern. Parameters such as gain, matching, noise, voltage and temperature coefficients, power dissipation, resistance and the analog/digital interface are especially crucial if there are different internal supply voltages. Additionally, parasitic devices and effects, such as crosstalk and substrate noise, and interface issues with the environment (e.g., electromagnetic compatibility) are major design challenges. Each device in the analog world must be carefully characterized and modeled across a very large parameter space to ensure a reliable circuit design. A wide range of statistical models is needed, such as worst-case models, statistical corner models and Monte Carlo mismatch models, to enable circuit design sizing and design-centering techniques that achieve high-yielding, robust designs.
Extensive verification routines are crucial in the design flow to guarantee the analog/mixed-signal design functions well, can be manufactured and is reliable. These verification routines must include safe operating area (SOA) checks for HV MOS transistors, pre- and post-layout parasitic extraction, design rule checks (DRC), layout versus schematic (LVS) routines and electrostatic discharge (ESD) checks.
In addition, the foundry must support a wide range of electronic design automation (EDA) platforms, enabling designers to choose best-in-class tools for optimizing their design flows. Setting up such a comprehensive design support and process characterization ecosystem is a major precondition for a successful analog foundry.
Although reusable IP is available on the digital side, reusing IP in the analog world that deals more with the physics of the design is far more difficult. It is necessary though for analog designers to be able to reuse their IP to shorten design time, given the smaller volumes and design complexity.One established solution for dealing with this type of problem is having the foundry provide a wide range of analog IP optimized for its processes. Analog IP provided by an analog foundry should comprise digital and I/O libraries, and analog building blocks such as bandgap, bias cells and NVM macrocells.