153 entries
Published: January 2010

Get an overview of the optical functions and features available as part of X-FABs More-than-Moore technology offering, including the impacts on spectral sensitivity, signal bandwidth, and noise margins. Explore what you need to consider when starting to design your optical product.


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Published: November 2009

Long-term functionality of integrated circuits (ICs) is based on the reliable operation of each component. Semiconductor device reliability within an IC is dependent on the specific stress mission profile of the ICs' intended application and its operating conditions. Shrinking primitive device dimensions and extended operating conditions compound the environmental challenges that designers face in trying to predict chip reliability.


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Published: October 2009

At high temperature, designers are faced with additional technological and design challenges. These issues and how to address them are discussed in this presentation. The webinar looks at X-FAB's high temperature solutions, in particular its latest High Temperature Modular CMOS process (XA035), a comprehensive CMOS offering with High Voltage (HV), RF, and EEPROM integration that is suitable for temperatures up to 175C. The presentation also covers high temperature modelling, application specific reliability and design for reliability.


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Published: October 2009

X-FAB steps beyond logic and memory scaling to deliver “More than Moore” value for customers. Instead of following Moore’s Law, X-FAB integrates technology features that interact with the analog world, and provides a comprehensive design ecosystem. It includes services and tools for developing diversified power/HV, MEMS, opto and analog products; a 24-hour technical hotline service; a portfolio of technically mature, extensive libraries and IP; a broad spectrum of primitive devices; and flexible prototyping options – all backed by X-FAB’s 15 years of solid analog/mixed-signal foundry expertise.


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Published: October 2009

In this paper we describe a novel tool for modeling the fabrication of MEMS and semiconductor devices, and show some examples of its application in the MEMS foundry business. The tool allows an accurate visualization of the step-by-step crreation of the final 3-D device geometry by using the 2-D layout and a description of the fabrication process.


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Published: August 2009

One time programmable (OTP) electrically programmed read only memory (EPROM) become a simple low cost solution in non-volatile memory (NVM) to be integrated in variety of CMOS baseline technology node platforms without extra masks or additional process cost incur. The feasibility of EPROM floating gate built on buried channel pMOSFET was explored experimentally. The buried channel device physic fundamental characteristics would lead to consistently high erased cell current (Ioff) in μA level instead of expected pA level for EPROM cell in erased state. Alternative external voltage biasing could not be applied due to unavailability of floating gate terminal connection to control the buried channel onoff state.


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Published: August 2009

OLED-on-CMOS micro-displays are widely studied in the recent years due to the fast development of OLED. However, there are some challenges to fabricate the electrodes of OLED. In this study, the process challenges are discussed, and the surface roughness is suggested to be one of the critical parameters.


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Published: August 2009

Resistance of contacts on nonsalicided active must be sufficiently low in order for a device to function. The objective of the work presented here is to discuss steps taken to reduce initially high contact resistance on non-salicided active of a high breakdown voltage transistor to meet functional requirement. In order to create a special 30V high voltage transistor in a NAND flash device, the active region between gate and junction has to be non-salicided. Therefore, the contact resistance needs to be lowered down by other means. This paper shows substantially reduction in contact resistance value and better resistance distribution uniformity across a wafer through a combination of plug implant and improved contact etching with O2 flush condition and additional oxide etching.


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Published: August 2009

This study was carried out to investigate the bimodal distribution of Vt (threshold voltage) of 3.3V differential pair PMOS structure within a wafer in which the abnormal transistor shows half lower than normal threshold voltage value and higher off state leakage current. The root cause was identified by simulation which is increasing gate oxide thickness of thin gate oxide area and finally matches behavior of the abnormal transistor with low threshold voltage and high off state leakage. The solution was implemented with O2 descum process into the dual gate oxide process flow, which O2 descum process was inserted after photo resist patterning for thick gate oxide in order to remove potential thin photo resist scum which is blocking wet etch reaction to oxide and causes thick gate oxide to remain at the thin gate oxide area. Details evaluation, measurement and result will be further discussed.


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Published: August 2009

In SOC (System on Chip) technology, the various types of devices located on an IC chip typically have different operating voltages thus requiring multiple gate oxide layers of different thickness to be formed. In order to form different gate oxide, several oxide removal and growth steps have to be carried out which make the process more complex and particularly have a detrimental impact on the Shallow Trench Isolation (STI) structures.


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