150 entries
Published: July 2010

A novel 0.18μm 200V integrated technology based on Partial SOI and lateral Super Junctions devices is presented. The dielectric isolation inherent in SOI allows simple and areaefficient integration of electrically floating CMOS and HV devices while removing all substrate carrier injection-related parasitic effects. The Super Junctions give a competitively low on-resistance of HVMOS and provide a wide-range breakdown voltage-scaling capability.


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Published: April 2010

The integration of full custom analog circuitry into a silicon chip, to provide cost-effective products, requires a full understanding of the process architecture and uses completely different methods compared with those used for digital designs. This webinar briefly covers the digital design arena before entering into in-depth discussion of analog layout techniques. It explores the integration of X-FAB-supported primitive devices into complex integrated chips in detail, including diffusions, wells and associated layers that can be merged. The session also covers derivation of "well" combinations from the design layers, and gives guidelines for high-voltage interconnects across these well regions to avoid parasitic leakage paths.


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Published: April 2010

The exponential growth of opto-electronic applications such as digital cameras and mobile phones during the past few years has followed the same Moore’s Law scenario as memories and digital gates did in the past. These low-cost, high-volume applications require highly specialized fabs and processes to achieve the lower node size that allows for higher pixel count and higher resolution. Moore’s Law works very well for these high-volume applications. However, it falls short for several other applications that require the integration of various opto-sensitive components. These applications might have varying technical requirements for sensitivity, supported wavelength, noise and bandwidth; and commercial volume requirements spanning from low to high. In addition, many Silicon on Chip (SoC) solutions also require multiple analog functions, including opto-electronic sensors. Highly specialized fabs that follow Moore’s Law simply lack the flexibility to support all of these different requirements.


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Published: April 2010

The high voltage device can be embedded into conventional shallow trench isolation (STI) logic process. Basically, SVX (Smart Voltage Extension) technique was applied in order to integrate 32V high voltage LDMOS into a standard 0.18 micron low voltage CMOS technology without any process change. However, a double hump issue was being observed in high voltage LDNMOS. The double hump phenomenon is mainly occurs due to lower threshold voltage of transistor corner that will lead to high sub-threshold leakage. This paper presents a solution by applying boron implant in HV LDNMOS to suppress the double hump issue. The retrograde baseline CMOS p-well implant is used for this purpose to avoid an additional mask and process step.


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Published: April 2010

An experiment in base and pedestal collector implant has been conducted to study the impact and further improve the performance of a 0.6 micron silicon poly emitter bipolar transistor. It has been shown the bandwidth can be improved form 13GHz to 15GHz with acceptable changes to the other bipolar performances.


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Published: March 2010

For the first time, this paper demonstrates the experimental results for two types of test structures of field transistors up to 200°C. The field transistor structures which are stripe (conventional) and square ring (new) structures were measured and investigated in term of field leakage current and onstate characterization at high temperature.


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Published: March 2010

Sub-wavelength structures in metal films have interesting optical properties that can be implemented for sensing applications: gratings act as wire grid polarizer, hole arrays with enhanced transmission can be used as spectral filters. This paper demonstrates the feasibility of these nanostructures using 180 nm and 90 nm complementary metal-oxide semiconductor (CMOS) processes. The metal layers of the process can be used for optical nanostructures with feature sizes down to 100 nm.


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Published: January 2010

Get an overview of the optical functions and features available as part of X-FABs More-than-Moore technology offering, including the impacts on spectral sensitivity, signal bandwidth, and noise margins. Explore what you need to consider when starting to design your optical product.


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Published: November 2009

Long-term functionality of integrated circuits (ICs) is based on the reliable operation of each component. Semiconductor device reliability within an IC is dependent on the specific stress mission profile of the ICs' intended application and its operating conditions. Shrinking primitive device dimensions and extended operating conditions compound the environmental challenges that designers face in trying to predict chip reliability.


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Published: October 2009

At high temperature, designers are faced with additional technological and design challenges. These issues and how to address them are discussed in this presentation. The webinar looks at X-FAB's high temperature solutions, in particular its latest High Temperature Modular CMOS process (XA035), a comprehensive CMOS offering with High Voltage (HV), RF, and EEPROM integration that is suitable for temperatures up to 175C. The presentation also covers high temperature modelling, application specific reliability and design for reliability.


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