23 entries, filtered by: Wafer Manufacturing
Published: September 2002

Wafer bonding is an basic process in nearly all technologies for industrial MEMS production. To the one wafer bonding is used to pre-process substrates with buried layers, to make special micromachining processes possible. On the other hand wafer bonding is necessary for zero level packaging, the encapsulation and sealing of free moveable structures and cavities on wafer level. The wafer bonding steps of industrial used technologies have to be very reproducible and safer to ensure an economical use by sufficient high yield.


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Published: October 2003

The importance of surface micromachining processes has increased over the last few years. After the fundamental problems of these technologies have been solved in research institutes, surface micromachined components now arrive in industrial production, e.g. inertial sensors for automotive applications. In comparison to the classical bulk micromachined components, technologies based on surface micromachining provide a wide range of advantages.


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Published: May 2004

This paper reports on glass frit wafer bonding, which is a universally usable technology for wafer level encapsulation and packaging. After explaining the principle and the process flow of glass frit bonding, experimental results are shown. Glass frit bonding technology enables bonding of surface materials commonly used in MEMS technology. It allows hermetic sealing and a high process yield. Metal lead throughs at the bond interface are possible, because of the planarizing glass interlayer. Examples of surface micromachined sensors demonstrate the potential of glass–frit bonding.


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Published: October 2006

Conventional I-line lithography process utilizes single post-apply bake temperature to unify and simplify the process. As design rule shrinks and mask field size increases, tighter specification is applied on non-critical implant layers, including thick implant resist with thickness typically 4.0 mum and above. Poor uniformity for CD & overlay was observed for thick implant resist layer. Systematic uncorrectable overlay residue was observed from the overlay map.


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Published: September 2007

Using silicon-based MEMS technologies, the cost-efficient production of gyroscopes has become possible in recent years. As a result, gyroscopes are entering new markets, such as for highly accurate GPS-Instruments where the gyroscope enhances accuracy in situations where satellite reception is lost, for example in tunnels. However, since all gyroscopes are very precise resonating measurement devices, this leads to stringent wafer processing requirements for their production.


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Published: November 2008

The fast scanning mechanism of High Current batch Implanter is achieved by spinning the wafer disk with angular speed more than 1200 Rotation-Per-Minute (RPM). If particles hit device wafers during implant it can cause serious damage to device structure. Particle generation areas are mainly from Source terminal, Accelerator Column, Plasma Flood Gun (PFG) and beam line wall.


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Published: November 2008

Traditional cross-sectional sample treatment methods such as BOE (Buffered oxide etch), can easily highlight Titanium Salicide (TiSi2) by etching away the TiSi2 (thus creating voids or cavitations) with no impact on the silicon underneath the salicide. However, this method does not work for devices using Cobalt Salicide (CoSi2) technology. The work presented here is to introduce a special etchant or chemical mix that will etch the Cobalt Salicide (CoSi2), with no significant impact on the silicon underneath the salicide layer.


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Published: July 2009

This paper presents an investigation of low oxide breakdown voltage on polysilicon-oxide-diffusion (POD) capacitor. The dielectric was 7 nm thermal oxide which was grown simultaneously for MOS transistor as gate oxide. The V-Ramp measurement showed bimodal distribution of Vbd with one circular patch having < 7 V instead of the target Vbd (10 V). The size of the patch depends on the POD capacitor area. This behavior was not observed on gate oxide of MOS transistor and 22.5 nm POD capacitor. Process partition check, including wafer orientation and wafer slot arrangement was conducted. The specific process step causing the patch signature has been identified successfully.


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Published: November 2010

This paper suggests an improved method to round off the concave corners of the deep trenches formed by plasma etch. The corner rounding technique, sacrificial oxidation (SACOX) before gate oxidation, has been practiced on the shallow trench isolation (STI) to improve the CMOS leakage performance.


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Published: September 2011

For the Synchronous DC-DC converter switching performance of low-voltage power MOSFETs, the gate-drain charge density (Qgd) is an important parameter. The so-called figure-of-merit, which is defined as the product of the specific on-resistance (Ron.sp) and Qgd is commonly used to quantify the switching performance for a specified off-state breakdown voltage (BVds).


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