31 entries, filtered by: Characterization
Published: September 2011

Using a trench isolated 650V quasi-vertical n-channel DMOS as a starting point several new 650V transistor types have been evaluated. Mainly by design measures a 650V depletion DMOS, a 650V PMOS and a 650V IGBT were created for a modular integration into the process flow.


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Published: July 2011

In low leakage MOS device fabrication, careful pn junction design is critical to control overall device leakage, such as Band-To-Band Tunneling (BTBT) and Gate-Induced Drain Leakage (GIDL) that are always taken into consideration by device designers. Source/Drain implantation also play a very important role in suppressing silicon dislocation effect, which increases implanted species transient-enhanced diffusion (TED) and induces shallow-junction leakage.


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Published: July 2011

An enhancement-mode Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) device has been developed in 0.13μm technology platform. The single-transistor (1-T) SONOS device in NOR Flash memory array utilizes n-channel cells. The development of 1-T SONOS is not an easy feat due to many disturbs experienced by the cells during operation.


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Published: May 2011

Successful integration of 100V LDMOS devices in 0.35μm CMOS technology is presented in this paper. These integrated devices are enhanced N-type and P-type LDMOS which are compatible with thin (14nm) and thick (40nm) layers of gate oxide. A breakdown voltage of more than 100V with RDS (ON) =200/180mΩ.mm2 for N-type LDMOS and RDS (ON) =690/640mΩ.mm2 for P-type LDMOS with 14nm/40nm gate oxide thickness.


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Published: March 2011

A study has been carried out to improve metal-insulator-metal (MIM) capacitor's capacitance density and linearity performance. The scopes of the study included single MiM and stack MIM structures. Different dielectric schemes were evaluated with their corresponding capacitance density, breakdown voltages and linearity coefficient to voltage and temperature variation etc. characterised.


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Published: March 2010

For the first time, this paper demonstrates the experimental results for two types of test structures of field transistors up to 200°C. The field transistor structures which are stripe (conventional) and square ring (new) structures were measured and investigated in term of field leakage current and onstate characterization at high temperature.


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Published: August 2009

One time programmable (OTP) electrically programmed read only memory (EPROM) become a simple low cost solution in non-volatile memory (NVM) to be integrated in variety of CMOS baseline technology node platforms without extra masks or additional process cost incur. The feasibility of EPROM floating gate built on buried channel pMOSFET was explored experimentally. The buried channel device physic fundamental characteristics would lead to consistently high erased cell current (Ioff) in μA level instead of expected pA level for EPROM cell in erased state. Alternative external voltage biasing could not be applied due to unavailability of floating gate terminal connection to control the buried channel onoff state.


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Published: August 2009

This study was carried out to investigate the bimodal distribution of Vt (threshold voltage) of 3.3V differential pair PMOS structure within a wafer in which the abnormal transistor shows half lower than normal threshold voltage value and higher off state leakage current. The root cause was identified by simulation which is increasing gate oxide thickness of thin gate oxide area and finally matches behavior of the abnormal transistor with low threshold voltage and high off state leakage. The solution was implemented with O2 descum process into the dual gate oxide process flow, which O2 descum process was inserted after photo resist patterning for thick gate oxide in order to remove potential thin photo resist scum which is blocking wet etch reaction to oxide and causes thick gate oxide to remain at the thin gate oxide area. Details evaluation, measurement and result will be further discussed.


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Published: August 2009

Monolithically integrated photodiodes with high spectral responsivity over the entire visible and the near infrared spectral range are of growing interest for the semiconductor industry, since the next generation of optical data storage devices (Blue DVD) will soon be brought to market. In this paper, the bandwidth of photodiode dependence on the junction implant conditions and thermal budget was simulated by TCAD. It shows significant dependence on these process conditions. The corresponding mechanism related to RC delay, relationship between depletion region and light absorption will be discussed in detail with the help of simulation pictures and simple model explanation.


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Published: May 2008

The long term isolation properties of deep trenches in thick SOI have been investigated by current-voltage characteristics. A strong change of the measured trench leakage current was observed depending on the applied voltage. Further on a marked decrease of the leakage current was observed depending on the duration and polarity of the applied stress.


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