18 entries, filtered by: Simulation
Published: June 2015

Reducing power consumption is unquestionably a top priority for analog/mixed-signal designs due to growing demand for battery-powered mobile applications. Responding to this need, X-FAB will offer a free webinar worldwide. This webinar explains how a unique combination of technology – a CPF/UPF (Common / Unified Power Format) design specification and X-FAB’s digital standard cell libraries – makes low-power designs more reliable and reusable.
Come find out how to prepare and apply low-power design specifications with CPF and UPF standards that can help shorten design cycles and reduce errors at each design stage. Also learn how X-FAB’s digital standard cells with multi-voltage/ power shut-off are implemented, and how they work together with a power aware tool chain to enhance low power design flows.
X-FAB’s reference kit supports fast and easy adoption of such power aware design flows by providing a realistic design and detailed documentation.


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Published: September 2014

For a high robust metallization it is necessary to solve different problems related to migration mechanisms and thermo-mechanical stress in the material. Extended operating conditions and challenging assembling processes influence stress behaviour in chip corners. Typically the corner area of the chip is excluded for use. For higher stress load the forbidden area increases. But effort for demanding mission profiles of a product should not cumulative in increasing chip size. Simulation can help to a better understanding of mechanical stress in the chip corner and chip-package interaction.


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Published: September 2014

The miniaturization process of CMOS components creates new challenges for the development of integrated circuits. Especially the connections with a tungsten via between two metal layers can be a problem. Changes in geometry can bear on reliability problems. For a robust metallization design it is necessary to know, how strong the influence of the tungsten via alignment affects the physical behavior. 


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Published: June 2014

For industrial and automotive applications a 0.35μm aluminium CMOS process is one of the common used technologies. An increasing demand on extended operating conditions must be fulfilled especially for high current carrying metal lines. A new design concept is to modify the shape of these lines. The use of slots especially of octahedron slots demonstrates a better robustness towards electromigration in upper metallization layers. Another benefit is the good reliability under pulsed DC conditions primarily in comparison to wide homogeneous filled metal lines.


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Published: April 2012

The article at hand presents the results of thermoelectrical simulations of migration effects in integrated interconnect systems in comparison to measurement data. The simulation concept will be described and the output values as mass flux divergence and time-to-failure (TTF) will be discussed.


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Published: November 2009

Long-term functionality of integrated circuits (ICs) is based on the reliable operation of each component. Semiconductor device reliability within an IC is dependent on the specific stress mission profile of the ICs' intended application and its operating conditions. Shrinking primitive device dimensions and extended operating conditions compound the environmental challenges that designers face in trying to predict chip reliability.


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Published: June 2009

A combination of conventional cross sectional process and device simulations combined with top down and 3D device simulations have been used to design and optimise the integration of a 100V Lateral DMOS (LDMOS) device for high side bridge applications. This combined simulation approach can streamline the device design process and gain important information about end effects which are lost from 2D cross sectional simulations. Design solutions to negate detrimental end effects are proposed and optimised by top down and 3D simulations and subsequently proven on tested silicon.


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Published: November 2008

The work presented here show the impact of different reticle transmission ratio (macro pattern density) to metal profile and CD bias of metal etch process. These impacts are due to macro loading and passivation effects differ when pattern density at wafer level changed. We also try to investigate the impact of passivation gas to above phenomenon.


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Published: November 2008

The work presented here shows a change in migration behaviour of a transferred AlCu metallization system. Different failure mechanisms in metallization are known. Migration effects like electro-, thermo- and stress migration are the main failure mechanisms in a metallization. This study shows the detection and exploration of a significant change in the migration mechanism of a wide lines of a top level interconnect of a standard metallization. The study demonstrates the differences of the transferred metallization system and the influence for the degradation behaviour and reliability.


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Published: July 2008

With the further scaling down of CMOS devices, hot carrier induced degradation has become one of the most important reliability concerns. In the hot carrier effect, carriers are accelerated by the channel electric fields and become trapped in the oxide. These trapped charges cause time dependent shifts in measured device parameters.


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