116 entries
Published: December 2012

This paper evaluates the technique used to improve the latching characteristics of the 200V n-type superjunction (SJ) LIGBT on partial SOI. The initial design latches at about 23V with forward voltage drop (VON) of 2V at 300A/cm2. The latest design shows increase of latch-up voltage close to 100V without significant expense of VON.


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Published: December 2012

The fabrication of semiconductor devices, even in the area of customer oriented business, is one of the most complex production tasks in the world. A typical wafer production process consists of several hundred steps with numerous resources like equipments and operating staff. The optimal assignment of each resource at each time for a certain number of wafers is vital for a efficient production process. Several demands defined by the customers and facility management must be taken into consideration with the objective to find the best tradeoff between the different needs.


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Published: December 2012

The XH018 series is X-FAB’s 0.18 micron Modular Mixed Signal HV CMOS Technology. Based upon the industrial standard single poly with up to six metal layers 0.18 micron drawn gate length N-well process, integrated with highvoltage and Non-Volatile-Memory modules, the platform is ideal for SOC applications in the automotive market, as well as emdedded high-voltage applications in the communications, consumer and industrial market.
Comprehensive design rules, precise SPICE models, analog and digital libraries, IPs and development kits support the process for major EDA vendors.


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Published: November 2012

Are you challenged with having to design a device that requires bidirectional isolation and has several voltage levels integrated on a single chip without latch-up? If that is the case, you should join our upcoming webinar introducing XT018, the world’s first trench-isolated SOI (silicon on insulator) foundry technology offering for 200V MOS capability at 180nm. The presentation covers the general benefits and trade-offs of using SOI technology vs. a silicon bulk process. It highlights features such as super-junction architecture for 100V to 200V devices with complete dielectric isolation, the possibility to apply defined handle wafer potentials, and a highly flexible modular approach for selecting specific technology features that meet your exact needs.


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Published: October 2012

This Inter-poly Oxide-Nitride-Oxide (ONO) dielectric film has been widely used as dielectric films in stacked gate Flash memory devices. The ONO dielectric film plays an important role in ensuring good reliability in flash memory devices. In this paper, the characteristics of ONO dielectric films have been analyzed.


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Published: October 2012

In this paper, optimization and physical scaling of the SONOS ONO triple layer are extensively evaluated, with detailed characterization of the Flash cell behavior. Reliability tests have demonstrated high temperature endurance and long-term data retention. The results have shown that the reliability requirement is attainable even with down scaling of the vertical component of the oxynitride charge trapping layer, which makes it feasible to operate the cell at a lower programming voltage.


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Published: October 2012

By this article an introduction of a highly robust metal track layout especially suitable for high current and temperature applications will be introduced. Starting with the reliability limitations normally observed for wide metal tracks, conclusions regarding the requirements for robust layout techniques will be drawn.


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Published: October 2012

This paper presents a comparison between the superjunction LIGBT and the LDMOSFET in partial silicon-on-insulator (PSOI) technology in 0.18µm PSOIHV process. The superjunction drift region helps in achieving uniform electric field distribution in both structres but also contributes to the on-state current in the LIGBT.


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Published: September 2012

Gate oxide early breakdown was investigated. It was verified that the gate oxide quality is good and failure was due to extrinsic causes. The failure, which was localized at the edge of LOCOS was similar to Kooi effect. However, investigations showed that it was due to nitridation occured during high temperature nitrogen anneal. Investigation methods to find the root cause of failure were explained. Alternative methods to solve the failure were explored; including thickening the sacrificial oxide layer and changing the nitrogen anneal process sequence. Final solution was chosen based on PCM stress test, QBD and TDDB result with minimal process change.


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Published: September 2012

Reliability tests assessment are used to evaluate the quality of different process schemes of MIM capacitors. Typically, VRAMP tests can be used to check for extrinsics; which are common and popular method used for evaluating yield issues and early life failures (in which the product failures in ppm level); while TDDB tests are used to determine the intrinsic quality of the capacitor dielectrics; thus the lifetime will be extrapolated accordingly from its dependency from accelerated tests at different higher stress conditions down to the corresponding use condition.


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