172 entries
Published: June 2014

First-time-right in analog design depends not only on proper consideration of process variations and design sensitivities but also on device reliability. Device aging can jeopardize performance and long-term product success and therefore should be taken into account as early as possible in the development. This webinar provides an overview of reliability physics and considerations and gives guidance on reliability conscious circuit design. Critical issues are discussed and future options for a reliability-aware design flow are indicated.


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Published: June 2014

For industrial and automotive applications a 0.35μm aluminium CMOS process is one of the common used technologies. An increasing demand on extended operating conditions must be fulfilled especially for high current carrying metal lines. A new design concept is to modify the shape of these lines. The use of slots especially of octahedron slots demonstrates a better robustness towards electromigration in upper metallization layers. Another benefit is the good reliability under pulsed DC conditions primarily in comparison to wide homogeneous filled metal lines.


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Published: November 2013

The XH035 series is X-FAB’s 0.35-micron Modular RF capable Mixed Signal Technology. Main target applications are standard cell, semi-custom and full  custom designs for Industrial, Automotive and Telecommunication products. Based on a single poly, triple metal 0.35-micron drawn gate length process for digital applications, process modules are available such as embedded Non-Volatile Memory, high voltage options, as well as standard or thick fourth layer metal, double-poly and MIM capacitor and high resistance polysilicon.


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Published: October 2013

Is there magic that makes analog designs successful? How can designs achieve ESD (electro-static discharge) specifications? Do DFM methods make designs more robust? This webinar answers these questions and provides tips & tricks for analog design.


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Published: October 2013

This webinar session provides guidance through the EDA environment and describes the interaction among EDA tools, design methodology and PDKs to optimize the design process. It uses selected reference flows and best practice examples for critical components during the design phase.


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Published: September 2013

This webinar session focuses on the importance of proper characterization data for successful analog design, and discusses how modeling and process characterization can make life easier for analog design engineers. It covers statistic modeling approaches, model quality assurance and process calibration.


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Published: September 2013

Showing first-time-right performance statistics from X-FAB's customer base, this first session outlines the challenges involved in achieving first-time-right analog designs. It talks about what impact the choice of process architecture makes, and discusses the pros and cons of different process architectures including SOI and BCD.


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Published: July 2013

For most devices sitting on SOI wafer, there is a consideration of backside coupling effect. This phenomenon becomes catastrophic if the device sits on the SOI wafer is an IGBT which consists n-p-n-p structure and employs both the partial SOI and DTI technique. Earlier leakage had been found during development of 200V superjunction lateral IGBT (SJ LIGBT) on partial SOI.


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Published: July 2013

XDH10 is X-Fab´s dielectric trench insulated smart power technology. Main target applications are analog switch ICs, driver ICs for capacitive, inductive and resistive loads and EL / piezo driver ICs for applications using 220V net supply. The typical breakdown voltage of the HV DMOS devices is >350V or >650V. The modular process combines DMOS, bipolar and CMOS processing steps that are compatible with dielectric insulation to provide a wide variety of MOS and bipolar devices with different voltage levels within a dielectric bi-directional high voltage trench insulation on the same die.


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Published: June 2013

Lifetime determination is one of the reliability key tasks to have an accurate estimation of the period of time that can still survive with a certain confidence level under the specific operating conditions to perform the respective function of the applications. Various reliability tests have been designed to reveal and assess the respective wear-out degradation mechanisms.


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