28 entries, filtered by: SOI
Published: January 2013

Classical high voltage devices fabricated on SOI substrates suffer from backside coupling effect which could result in premature breakdown. This phenomenon becomes more prominent if the structure is an IGBT which features a p-type injector. To suppress the premature breakdown due to crowding of electro-potential lines within a confined SOI/buried oxide structure, the partial SOI (PSOI) technique is being introduced. This paper analyzes and characterizes the off-state behaviour of an n-type Superjunction (SJ) LIGBT fabricated on PSOI substrates.


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Published: December 2012

This paper evaluates the technique used to improve the latching characteristics of the 200V n-type superjunction (SJ) LIGBT on partial SOI. The initial design latches at about 23V with forward voltage drop (VON) of 2V at 300A/cm2. The latest design shows increase of latch-up voltage close to 100V without significant expense of VON.


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Published: November 2012

Are you challenged with having to design a device that requires bidirectional isolation and has several voltage levels integrated on a single chip without latch-up? If that is the case, you should join our upcoming webinar introducing XT018, the world’s first trench-isolated SOI (silicon on insulator) foundry technology offering for 200V MOS capability at 180nm. The presentation covers the general benefits and trade-offs of using SOI technology vs. a silicon bulk process. It highlights features such as super-junction architecture for 100V to 200V devices with complete dielectric isolation, the possibility to apply defined handle wafer potentials, and a highly flexible modular approach for selecting specific technology features that meet your exact needs.


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Published: October 2012

This paper presents a comparison between the superjunction LIGBT and the LDMOSFET in partial silicon-on-insulator (PSOI) technology in 0.18µm PSOIHV process. The superjunction drift region helps in achieving uniform electric field distribution in both structres but also contributes to the on-state current in the LIGBT.


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Published: September 2012

Ever been stuck with the “one product, one process” rule when what you really needed was access to a world-class quality process for multiple applications? Not anymore.
X-FAB is presenting a webinar on its open-platform MEMS inertial sensor processes including its new 3D inertial sensor technology. Learn how you can use X-FAB’s design partner, MicroMountains Applications, or apply your own design to X-FAB’s ready-to-use processes to run high or low wafer volumes without long and costly process development. Find out how X-FAB can help you get to market faster and secure high-quality manufacturing for inertial sensors. You’ll get an overview of both inertial sensor technologies and IP blocks from X-FAB, as well as design and test support from MicroMountains Applications.


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Published: June 2012

This paper demonstrates and discusses novel “three dimensional” silicon based junction isolation/termination solutions suitable for high density ultra-low-resistance Lateral Super-Junction structures.


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Published: May 2012

XDM10 is X-Fab´s dielectric trench insulated smart power technology. Main target applications are analog switch ICs, driver ICs for capacitive, inductive and resistive loads and EL / piezo driver ICs for applications using 110V net supply. The typical breakdown voltage of the HV-DMOS devices is >350 V or >275V. The modular process combines DMOS, bipolar and CMOS processing steps that are compatible with dielectric insulation to provide a wide variety of MOS and bipolar devices with different voltage levels within a dielectric bi-directional high voltage trench insulation on the same die.


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Published: June 2011

In this paper, micromachined acceleration sensors as ready-to-use Intellectual-Property-Blocks (IP-Blocks) are introduced. These standard elements are available for a special surface micromachining foundry technology. They are ready to use, characterized and qualified design elements, which can be customized by changing the peripheral elements such as bond pads, and allow the fast prototyping and production start of high-performance inertial sensors.


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Published: May 2011

This paper demonstrates and explains the effects of hot carrier injection and interface charge trapping correlated with impact ionization under normal on-state conditions in a highly dense low-resistance Super-Junction LDMOSFET. The study is done through extensive experimental measurements and numerical simulations using advanced trap models.


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Published: May 2011

In this paper we present a modular trench isolated high voltage SOI process with the possibility to integrate various types of high voltage transistors. The integration of these additional 650 V devices takes place in a modular approach which allows a high process flexibility to support different applications with a minimum number of additional or changed process steps.


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