5 entries, filtered by: ESD
Published: February 2016

Elevated levels of integration combined with growing demands for greater cost effectiveness in electronic system implementations (from automotive right through to consumer applications) are increasing the need for IC electro-static discharge (ESD) robustness at the system level. System level ESD is a concern when any IC pin is directly connected to the “outer world”. These external pins have to be able to withstand high energy ESD pulses or else the system's long term operation could be put at risk.
In the latest of its series of informative webinars, X-FAB will discuss the implementation of ESD protection regarding system-level ESD and high energy ESD pulses. It will cover the difference between component and system-level ESD protection, provide insights on how to apply characterization methods such as the Human Metal Model (HMM) and Long-Duration Transmission Line Pulsing (LD-TLP). The presenter will also share best practices for safeguarding against system-level ESD and high energy ESD pulses

Published: October 2013

Is there magic that makes analog designs successful? How can designs achieve ESD (electro-static discharge) specifications? Do DFM methods make designs more robust? This webinar answers these questions and provides tips & tricks for analog design.

Published: March 2012

Electrostatic discharge (ESD) is a serious threat to integrated circuits (ICs) that can cause irreversible damage. This webinar on ESD protection will show you solutions on how to eliminate ESD threats in complex analog/mixed-signal and high-voltage designs. It covers an overview of various ESD protection concepts, and explains the structures and schemes available to protect against electrostatic discharge in X-FAB’s enhanced 0.35 and 0.18 micrometer XH035 and XH018 high-voltage foundry processes. The webinar presentation also highlights similarities and differences among ESD protection concepts, outlining the advantages and disadvantages of each in circuit designs.

Published: September 2011

This paper presents a simple but effective way to improve an NMOS transistor’s ESD robustness for use in I/O pads. Simulation and physical failure analysis has been performed to identify the source of the ESD failure. Process splits have been performed primarily at LDD (Lightly Doped Drain) implant and salicidation process based on data presented in this paper.

Published: May 2008

The snapback trigger voltage of the NDMOS in a 0.18μm automotive smart power technology is strongly reduced at large gate bias. This behavior of the deep-submicron multiresurf NDMOS, which makes its ESD protection difficult and limits its electrical safe operating area, and the influence of various device modifications are investigated by TCAD simulation. SCR-based ESD protection schemes for I/O and power supply protection are presented. For supply protection the SCR is modified to increase its holding voltage. The ability to protect the NDMOS at non-zero gate bias is discussed.