116 entries
Published: December 2011

Looking for new improvement options such as new dispatching rules of an existing semiconductor fabrication facility, a detailed model is indispensable to check the data quality as well as detecting main influences of the facility and finally testing the new optimization approaches. In this paper, the whole way is described starting from the data acquisition and finishing with a appropriate model. In this study the modeling tool AnyLogic 6 is used. The model generation process show how important a reliable factory database is and shows first appendages of automated model generation. An other important fact presented is the verification of the model according to real factory performance indicators.


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Published: November 2011

The purpose of this paper is to study the order management flow currently implemented in supply chain of a semiconductor industry. There are various activities involved in a supply chain ranging from providing raw materials to the production of products, and also to ensure the delivery of the end products to customers. The main focus of a supply chain is to ensure that customers' orders are well-managed from the first day when the order is placed until the last day when the end products are ready to be delivered to customers. In other words, order fulfillment process (OFP) has to be practiced every time when customers place order.


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Published: November 2011

The power semiconductor industry has grown steadily in past two decades from $2.7 billion in 1992 and is expected to reach $13.1 billion in annual sales volume this year due to rapid proliferation of power electronics in many fields like telecommunication, automotive, new renewable energy system and energy conversion application. Among power transistor products, sales of modules built with Insulated Gate Bipolar Transistor (IGBT) are expected to increase 10 percent to $2.5 billion this year.
This paper gives an overview to different types of IGBTs available in current market as well as those under development.


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Published: September 2011

For the Synchronous DC-DC converter switching performance of low-voltage power MOSFETs, the gate-drain charge density (Qgd) is an important parameter. The so-called figure-of-merit, which is defined as the product of the specific on-resistance (Ron.sp) and Qgd is commonly used to quantify the switching performance for a specified off-state breakdown voltage (BVds).


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Published: September 2011

Wire Bond Shear (WBS) test is a method for evaluating the strength of a ball bond, to complement wire pull test. In foundry, wafer-level (WLR) WBS provides a quick way to demonstrate the integrity of metal bond pad, backend scheme as well as bond or via design. This is a big challenge for WLR WBS outsourcing as many of the factors affecting shear strength lying on the wire bonding parameters and shear test setup. This paper presents the outsourcing experiences of WBS tests and good shear strength was achieved from the outsource laboratory.


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Published: September 2011

A study on the effect of process fabrication for MIM capacitors analog matching performance was carried out, impacts from the MIM dielectrics, capacitor top and bottom metal materials, capacitor metal etch, wet cleaning, annealing process will be revealed by comparing the Pelgrom coefficients, i.e. the dependence of difference in capacitance of the matching pairs with respect to their corresponding square root of capacitor areas, the smaller the difference the better the matching.


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Published: September 2011

Diodes inherent in a CMOS process are light sensitive and could be exploited as photodetectors. To detect light the photo generated carriers need to be separated by the electrical field of an internal pn junction. They are either generated inside the depletion region or can get there by diffusion. The depth where these carriers are generated depends strongly on the wavelength. The generation profile, the pn junction depth and the diffusion length all impact the spectral sensitivity.


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Published: September 2011

This paper presents a simple but effective way to improve an NMOS transistor’s ESD robustness for use in I/O pads. Simulation and physical failure analysis has been performed to identify the source of the ESD failure. Process splits have been performed primarily at LDD (Lightly Doped Drain) implant and salicidation process based on data presented in this paper.


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Published: September 2011

Using a trench isolated 650V quasi-vertical n-channel DMOS as a starting point several new 650V transistor types have been evaluated. Mainly by design measures a 650V depletion DMOS, a 650V PMOS and a 650V IGBT were created for a modular integration into the process flow.


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Published: July 2011

In low leakage MOS device fabrication, careful pn junction design is critical to control overall device leakage, such as Band-To-Band Tunneling (BTBT) and Gate-Induced Drain Leakage (GIDL) that are always taken into consideration by device designers. Source/Drain implantation also play a very important role in suppressing silicon dislocation effect, which increases implanted species transient-enhanced diffusion (TED) and induces shallow-junction leakage.


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