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Sel. IP Name Category Provider Geometry Process Name Status Deliverable Description
axtoc01 * Crystal Oscillators
X-FAB
0.35 μm
XH035
PT
Layout
Schematic
Analog Library

XH035: A_CELLS. For MOS module only. axtoc01 is a robust 2 - 8 MHz crystal oscillator for supply voltage range from 2.4 to 3.6V. An external quartz crystal is required.

axtoc02 * Crystal Oscillators
X-FAB
0.35 μm
XH035
PT
Layout
Schematic
Analog Library

XH035: A_CELLS. For MOS module only. axtoc02 is a robust 32,768kHz crystal oscillatior for supply voltage range from 2.4 to 2.6V. An external quartz crystal is required.

aporc01 * Power on Reset
X-FAB
0.35 μm
XH035
PT
Layout
Schematic
Analog Library

XH035: A_CELLS. For MOS module only. aporc01 is a dynamic Power-on-Reset circuit. During power-on, POR output follows the supply voltage as long as it is below the threshold voltage. When the threshold voltage is reached, the POR signal turns low. A delay

aporc02 * Power on Reset
X-FAB
0.35 μm
XH035
PT
Layout
Schematic
Analog Library

XH035: A_CELLS. For MOS module only. aporc02 is a Power-on-Reset circuit with hysteresis. Reset signals are generated on both the rising and falling edge of the supply voltage. During power-on, POR output follows the supply voltage as long as it is b

aporc03 * Power on Reset
X-FAB
0.35 μm
XH035
PT
Layout
Schematic
Analog Library

XH035: A_CELLS. For MOS module only. aporc03 is a Power-on-Reset circuit. Reset signals are generated on both the rising and falling edge of the supply voltage. During power-on, POR output follows the supply voltage as long as it is below the threshold v

aregc01 * Voltage Regulator
X-FAB
0.35 μm
XH035
PT
Layout
Schematic
Analog Library

XH035: A_CELLS_HV. For MOS module only. aregc01 is a 5V/3.3V linear voltage regulator for up to 20mA load current. The regulator is powered viz its high voltage input.

aregc02 * Voltage Regulator
X-FAB
0.35 μm
XH035
PT
Schematic
Layout
Analog Library

XH035: A_CELLS_HV. For MOS module only. aregc02 is a 12V/3.3V linear voltage regulator for up to 20mA load current. The regulator is powered via its high-voltage input.

adrvc02 * Driver
X-FAB
0.35 μm
XH035
PT
Schematic
Layout
Analog Library

XH035: A_CELLS_HV. For MOS module only. adrvc02 is a driver circuit for external loads (relays, LEDs, etc). The circuit features PNOS open-drain output (high-side switch). The layout of adrvc02 makes it easy to incorporate in the flat IO ring.

adrvc03 * Driver
X-FAB
0.35 μm
XH035
PT
Schematic
Layout
Analog Library

XH035: A_CELLS_HV. For MOS module only. adrvc03 is a driver circuit for external loads (realys, LEDs, etc). The circuit features NMOS open-drain output (low-side switch). The layout of adrvc03 makes it easy to incorporate in the flat IO ring.

abiac04 * Bias
X-FAB
0.35 μm
XH035
PT
Schematic
Layout
Analog Library

XH035: A_CELLS_HV. For MOS module only. abiac04 is a high voltage bias cell. The circuit forces a current of 2µA (approx.) to flow through PHV with W/L ratio of 8µm/12µm and NHV with W/L ratio of 8µm/14µm.

arcoc07 * Oscillator
X-FAB
0.35 μm
XH035
PT
Schematic
Layout
Analog Library

XH035: A_CELLS_HV. For MOS module only. arcoc07 is a high-voltage 400kHz current-balancing RC oscillator with internal R and C. The cell features low temperature coefficient of clock frequency, constant duty cycle, and low power consumption.

LNA1 * LNA
X-FAB
0.35 μm
XH035
PT
Schematic
Layout
Analog Library

XH035: LNA Library: RF_LNA_CELLS. LNA1 is a broadband low noise amplifier. It should be bieased by the RF bias cell.

LNA2 * LNA
X-FAB
0.35 μm
XH035
PT
Schematic
Layout
Analog Library

XH035: LNA Library: RF_LNA_CELLS. LNA2 is a narrowband low noise amplifier. It should be biased by the RF bias cell.

DIV32 * Divider
X-FAB
0.35 μm
XH035
PT
Layout
Schematic
Analog Library

XH035: DIVIDER Library: RF_DIVIDER_CELLS. DIV32 is a Prescaler with a fixed ratio of 32. It should be biased by the RF bias cell.

BIAS * Bias
X-FAB
0.35 μm
XH035
PT
Schematic
Layout
Analog Library

XH035: BIAS Library: RF_BIAS_CELLS. BIAS is a bias cell intended for use with the various RF building blocks. It is based on a bandgap reference and voltage-to-current converters. Current biasing is preferable because of the higher immunity to interferenc

QCBGB10_35X Voltage Regulator
Bias
QualCore Logic, Inc.
0.35 μm
XH035
MP
GDSII
Schematic

Bandgap Voltage Reference and Current Bias Cell.

QCBIAS1_35X Current Reference
Bias
QualCore Logic, Inc.
0.35 μm
XH035
MP
GDSII
Schematic

Current Reference and Current Biasing Cell.

QCCMP4_35X Comparators
QualCore Logic, Inc.
0.35 μm
XH035
MP
GDSII
Schematic

Comparator Cell with N-Channel Inputs

QCDAC4_35X DAC
QualCore Logic, Inc.
0.35 μm
XH035
MP
GDSII
Schematic

Resistive String architecture.

QCOP4_35X Operational Amplifier
QualCore Logic, Inc.
0.35 μm
XH035
MP
GDSII
Schematic

Operational Amplifier Cell with P-Channel Inputs

QCOP5_35X Operational Amplifier
QualCore Logic, Inc.
0.35 μm
XH035
MP
GDSII
Schematic

Reference Amplifier

QCPOR4_35X Power on Reset
QualCore Logic, Inc.
0.35 μm
XH035
MP
GDSII
Schematic

Power On Reset cell

QCADB5_35X Other
QualCore Logic, Inc.
0.35 μm
XH035
PT
GDSII
Schematic

Connectivity IP. This is a product chip.

MR74039 Other
Moortec Semiconductor Ltd
0.35 μm
XH035
ID
GDSII
Verilog

The MR74039 is a fully integrated temperature sensor with a 12 Bit digital output designed in the XFab 0.35um XH035 process. It utilises a 12 bit Sigma Delta ADC for increased precision (0.25ºC). The temperature measurement range is fr

Sub 1dB LNA+mixer LNA
Mixer
Saul Research
0.35 μm
XH035
PT
GDSII
Schematic

LNA  and optional mixer based on XH035 process. Measured noise figure below 1dB including mixer. Described in a paper on the web site.  The techniques are readily applied to other processes.

Low Power DDS Other
Saul Research
0.35 μm
XH035
PT
GDSII
Schematic

Novel aproach to Direct Digital Synthesis, using a voltage-ladder reference. Accuracy is achieved by using a full resistor ladder array, so bit size equivalent to 12 bits has been shown. Prototypes using an 8 bit system are available on

Analogue SSB Chip Other
Saul Research
0.35 μm
XH035
PT
GDSII
Schematic

Very low power (3V, 25uA) 90 degree analogue phase shifter for SSB encoding/decoding. A full description is on the web site, with all measurements.

SA00AH8A00 ADC
Sony LSI Design Inc.
0.35 μm
XH035
ID
GDSII

SA00AH8A00 is a subranging 8-bit high-speed 50MS/s Analog-to-Digital Converter(ADC) for video band and disk servo use.

SA00AH8B00 ADC
Sony LSI Design Inc.
0.35 μm
XH035
ID
GDSII

SA00AH8B00 is a subranging  8-bit low-power 25MS/s Analog-to-Digital Converter(ADC) for disk servo use.

SA00PFC000 PLL
Sony LSI Design Inc.
0.35 μm
XH035
ID
GDSII

SA00PFC000 is a PLL with internal loop filter. Wide output clock freq. range : 10MHz~200MHz. Wide input clock freq. range : 2MHz~50MHz

 

MP = Mass ProductionPT = Prototyping, Silicon provenID = in DesignVS = Verified by Simulations (Soft-IP)

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